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Searched refs:mpc_mask (Results 1 - 25 of 34) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
166 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
168 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
224 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
226 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
252 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
254 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
256 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
258 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
260 reg->masks.field_region_end = mpc20->mpc_mask in mpc2_ogam_get_reg_field()
567 dcn20_mpc_construct(struct dcn20_mpc *mpc20, struct dc_context *ctx, const struct dcn20_mpc_registers *mpc_regs, const struct dcn20_mpc_shift *mpc_shift, const struct dcn20_mpc_mask *mpc_mask, int num_mpcc) dcn20_mpc_construct() argument
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H A Ddcn20_mpc.h267 const struct dcn20_mpc_mask *mpc_mask; member
274 const struct dcn20_mpc_mask *mpc_mask,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
253 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
255 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
257 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
259 reg->masks.field_region_end = mpc20->mpc_mask in mpc2_ogam_get_reg_field()
567 dcn20_mpc_construct(struct dcn20_mpc *mpc20, struct dc_context *ctx, const struct dcn20_mpc_registers *mpc_regs, const struct dcn20_mpc_shift *mpc_shift, const struct dcn20_mpc_mask *mpc_mask, int num_mpcc) dcn20_mpc_construct() argument
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H A Ddcn20_mpc.h267 const struct dcn20_mpc_mask *mpc_mask; member
274 const struct dcn20_mpc_mask *mpc_mask,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
107 const struct dcn201_mpc_mask *mpc_mask, in dcn201_mpc_construct()
118 mpc201->mpc_mask = mpc_mask; in dcn201_mpc_construct()
103 dcn201_mpc_construct(struct dcn201_mpc *mpc201, struct dc_context *ctx, const struct dcn201_mpc_registers *mpc_regs, const struct dcn201_mpc_shift *mpc_shift, const struct dcn201_mpc_mask *mpc_mask, int num_mpcc) dcn201_mpc_construct() argument
H A Ddcn201_mpc.h76 const struct dcn201_mpc_mask *mpc_mask; member
83 const struct dcn201_mpc_mask *mpc_mask,
H A Ddcn201_resource.c497 static const struct dcn201_mpc_mask mpc_mask = { variable
733 &mpc_mask, in dcn201_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.c42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
53 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) { in mpc32_mpc_init()
60 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { in mpc32_mpc_init()
143 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
145 reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc32_post1dlut_get_reg_field()
147 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
149 reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc32_post1dlut_get_reg_field()
152 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; in mpc32_post1dlut_get_reg_field()
154 reg->masks.field_region_end_slope = mpc->mpc_mask in mpc32_post1dlut_get_reg_field()
1020 dcn32_mpc_construct(struct dcn30_mpc *mpc30, struct dc_context *ctx, const struct dcn30_mpc_registers *mpc_regs, const struct dcn30_mpc_shift *mpc_shift, const struct dcn30_mpc_mask *mpc_mask, int num_mpcc, int num_rmu) dcn32_mpc_construct() argument
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H A Ddcn32_mpc.h331 const struct dcn30_mpc_mask *mpc_mask,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
180 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
182 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
185 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
187 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
189 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field()
191 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
194 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
196 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field()
198 reg->masks.field_region_end_base = mpc30->mpc_mask in mpc3_ogam_get_reg_field()
1436 dcn30_mpc_construct(struct dcn30_mpc *mpc30, struct dc_context *ctx, const struct dcn30_mpc_registers *mpc_regs, const struct dcn30_mpc_shift *mpc_shift, const struct dcn30_mpc_mask *mpc_mask, int num_mpcc, int num_rmu) dcn30_mpc_construct() argument
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H A Ddcn30_mpc.h999 const struct dcn30_mpc_mask *mpc_mask; member
1007 const struct dcn30_mpc_mask *mpc_mask,
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
170 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
172 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
175 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
177 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
179 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field()
181 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
184 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
186 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field()
188 reg->masks.field_region_end_base = mpc30->mpc_mask in mpc3_ogam_get_reg_field()
1384 dcn30_mpc_construct(struct dcn30_mpc *mpc30, struct dc_context *ctx, const struct dcn30_mpc_registers *mpc_regs, const struct dcn30_mpc_shift *mpc_shift, const struct dcn30_mpc_mask *mpc_mask, int num_mpcc, int num_rmu) dcn30_mpc_construct() argument
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H A Ddcn30_mpc.h599 const struct dcn30_mpc_mask *mpc_mask; member
607 const struct dcn30_mpc_mask *mpc_mask,
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
499 const struct dcn_mpc_mask *mpc_mask, in dcn10_mpc_construct()
510 mpc10->mpc_mask = mpc_mask; in dcn10_mpc_construct()
495 dcn10_mpc_construct(struct dcn10_mpc *mpc10, struct dc_context *ctx, const struct dcn_mpc_registers *mpc_regs, const struct dcn_mpc_shift *mpc_shift, const struct dcn_mpc_mask *mpc_mask, int num_mpcc) dcn10_mpc_construct() argument
H A Ddcn10_mpc.h131 const struct dcn_mpc_mask *mpc_mask; member
138 const struct dcn_mpc_mask *mpc_mask,
H A Ddcn10_resource.c447 static const struct dcn_mpc_mask mpc_mask = { variable
753 &mpc_mask, in dcn10_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
518 const struct dcn_mpc_mask *mpc_mask, in dcn10_mpc_construct()
529 mpc10->mpc_mask = mpc_mask; in dcn10_mpc_construct()
514 dcn10_mpc_construct(struct dcn10_mpc *mpc10, struct dc_context *ctx, const struct dcn_mpc_registers *mpc_regs, const struct dcn_mpc_shift *mpc_shift, const struct dcn_mpc_mask *mpc_mask, int num_mpcc) dcn10_mpc_construct() argument
H A Ddcn10_mpc.h131 const struct dcn_mpc_mask *mpc_mask; member
138 const struct dcn_mpc_mask *mpc_mask,
H A Ddcn10_resource.c383 static const struct dcn_mpc_mask mpc_mask = { variable
686 &mpc_mask, in dcn10_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_resource.c642 static const struct dcn30_mpc_mask mpc_mask = { variable
653 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn302_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_resource.c588 static const struct dcn30_mpc_mask mpc_mask = { variable
599 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn303_mpc_create()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c518 static const struct dcn20_mpc_mask mpc_mask = { variable
1372 &mpc_mask, in dcn21_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_resource.c604 static const struct dcn30_mpc_mask mpc_mask = { variable
1014 &mpc_mask, in dcn31_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn321/
H A Ddcn321_resource.c463 static const struct dcn30_mpc_mask mpc_mask = { variable
956 &mpc_mask, in dcn321_mpc_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c295 static const struct dcn20_mpc_mask mpc_mask = { variable
1091 &mpc_mask, in dcn21_mpc_create()

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