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Searched refs:mmVGT_ESGS_RING_SIZE_Sienna_Cichlid (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 macro
6816 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); in gfx_v10_0_check_grbm_cam_remapping()
6817 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); in gfx_v10_0_check_grbm_cam_remapping()
6820 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { in gfx_v10_0_check_grbm_cam_remapping()
6824 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); in gfx_v10_0_check_grbm_cam_remapping()
6890 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << in gfx_v10_0_setup_grbm_cam_remapping()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 macro
6920 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); in gfx_v10_0_check_grbm_cam_remapping()
6921 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); in gfx_v10_0_check_grbm_cam_remapping()
6924 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { in gfx_v10_0_check_grbm_cam_remapping()
6928 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); in gfx_v10_0_check_grbm_cam_remapping()
7008 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << in gfx_v10_0_setup_grbm_cam_remapping()

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