Searched refs:mmRLC_CP_SCHEDULERS_Sienna_Cichlid (Results 1 - 3 of 3) sorted by relevance
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mes_v10_1.c | 37 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 macro
1003 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); in mes_v10_1_kiq_setting()
1006 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in mes_v10_1_kiq_setting()
1008 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in mes_v10_1_kiq_setting()
|
| H A D | gfx_v10_0.c | 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 macro
6313 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); in gfx_v10_0_kiq_setting()
6316 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in gfx_v10_0_kiq_setting()
6318 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in gfx_v10_0_kiq_setting()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v10_0.c | 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 macro
6105 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); in gfx_v10_0_kiq_setting()
6108 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in gfx_v10_0_kiq_setting()
6110 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); in gfx_v10_0_kiq_setting()
|
Completed in 24 milliseconds