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Searched refs:mmDF_CS_AON0_DramBaseAddress0 (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/df/
H A Ddf_1_7_offset.h30 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/df/
H A Ddf_1_7_offset.h30 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Ddf_v1_7.c61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Ddf_v1_7.c61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c64 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 macro
933 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c63 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 macro
932 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()

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