| /kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/ |
| H A D | mtk_mt8183_mipi_tx.c | 48 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); in mtk_mipi_tx_pll_enable() local
52 dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_enable()
54 if (mipi_tx->data_rate >= 2000000000) { in mtk_mipi_tx_pll_enable()
57 } else if (mipi_tx->data_rate >= 1000000000) { in mtk_mipi_tx_pll_enable()
60 } else if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_enable()
63 } else if (mipi_tx->data_rate > 250000000) { in mtk_mipi_tx_pll_enable()
66 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_enable()
73 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); in mtk_mipi_tx_pll_enable()
75 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PW in mtk_mipi_tx_pll_enable()
90 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); mtk_mipi_tx_pll_disable() local
112 mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) mtk_mipi_tx_config_calibration_data() argument
132 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_on_signal() local
159 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_off_signal() local
[all...] |
| H A D | mtk_mipi_tx.c | 13 void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, in mtk_mipi_tx_clear_bits() argument
16 u32 temp = readl(mipi_tx->regs + offset); in mtk_mipi_tx_clear_bits()
18 writel(temp & ~bits, mipi_tx->regs + offset); in mtk_mipi_tx_clear_bits()
21 void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, in mtk_mipi_tx_set_bits() argument
24 u32 temp = readl(mipi_tx->regs + offset); in mtk_mipi_tx_set_bits()
26 writel(temp | bits, mipi_tx->regs + offset); in mtk_mipi_tx_set_bits()
29 void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, in mtk_mipi_tx_update_bits() argument
32 u32 temp = readl(mipi_tx->regs + offset); in mtk_mipi_tx_update_bits()
34 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset); in mtk_mipi_tx_update_bits()
40 struct mtk_mipi_tx *mipi_tx in mtk_mipi_tx_pll_set_rate() local
52 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); mtk_mipi_tx_pll_recalc_rate() local
59 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_on() local
74 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_off() local
91 mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx) mtk_mipi_tx_get_calibration_datal() argument
132 struct mtk_mipi_tx *mipi_tx; mtk_mipi_tx_probe() local
[all...] |
| H A D | mtk_mt8173_mipi_tx.c | 118 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); in mtk_mipi_tx_pll_prepare() local
122 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_prepare()
124 if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_prepare()
128 } else if (mipi_tx->data_rate >= 250000000) { in mtk_mipi_tx_pll_prepare()
132 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_prepare()
136 } else if (mipi_tx->data_rate > 62000000) { in mtk_mipi_tx_pll_prepare()
140 } else if (mipi_tx->data_rate >= 50000000) { in mtk_mipi_tx_pll_prepare()
148 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_prepare()
157 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CO in mtk_mipi_tx_pll_prepare()
208 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); mtk_mipi_tx_pll_unprepare() local
252 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_on_signal() local
265 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_off_signal() local
[all...] |
| H A D | mtk_mipi_tx.h | 40 void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
41 void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
42 void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask,
|
| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi.c | 16 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); in mtk_mipi_tx_pll_set_rate() local
18 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate); in mtk_mipi_tx_pll_set_rate()
20 mipi_tx->data_rate = rate; in mtk_mipi_tx_pll_set_rate()
28 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); in mtk_mipi_tx_pll_recalc_rate() local
30 return mipi_tx->data_rate; in mtk_mipi_tx_pll_recalc_rate()
35 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); in mtk_mipi_tx_power_on() local
39 ret = clk_prepare_enable(mipi_tx->pll_hw.clk); in mtk_mipi_tx_power_on()
44 mipi_tx->driver_data->mipi_tx_enable_signal(phy); in mtk_mipi_tx_power_on()
50 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); in mtk_mipi_tx_power_off() local
53 mipi_tx in mtk_mipi_tx_power_off()
67 mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx) mtk_mipi_tx_get_calibration_datal() argument
108 struct mtk_mipi_tx *mipi_tx; mtk_mipi_tx_probe() local
[all...] |
| H A D | phy-mtk-mipi-dsi-mt8183.c | 49 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); in mtk_mipi_tx_pll_enable() local
50 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_enable()
54 dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_enable()
56 if (mipi_tx->data_rate >= 2000000000) { in mtk_mipi_tx_pll_enable()
59 } else if (mipi_tx->data_rate >= 1000000000) { in mtk_mipi_tx_pll_enable()
62 } else if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_enable()
65 } else if (mipi_tx->data_rate > 250000000) { in mtk_mipi_tx_pll_enable()
68 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_enable()
81 pcw = div_u64(((u64)mipi_tx in mtk_mipi_tx_pll_enable()
91 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); mtk_mipi_tx_pll_disable() local
114 mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) mtk_mipi_tx_config_calibration_data() argument
134 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_on_signal() local
159 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_off_signal() local
[all...] |
| H A D | phy-mtk-mipi-dsi-mt8173.c | 124 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); in mtk_mipi_tx_pll_prepare() local
125 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_prepare()
129 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_prepare()
131 if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_prepare()
135 } else if (mipi_tx->data_rate >= 250000000) { in mtk_mipi_tx_pll_prepare()
139 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_prepare()
143 } else if (mipi_tx->data_rate > 62000000) { in mtk_mipi_tx_pll_prepare()
147 } else if (mipi_tx->data_rate >= 50000000) { in mtk_mipi_tx_pll_prepare()
196 pcw = div_u64(((u64)mipi_tx in mtk_mipi_tx_pll_prepare()
216 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); mtk_mipi_tx_pll_unprepare() local
256 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_on_signal() local
269 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); mtk_mipi_tx_power_off_signal() local
[all...] |