Home
last modified time | relevance | path

Searched refs:mg_pll_div1 (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h217 u32 mg_pll_div1; member
H A Dintel_dpll_mgr.c2971 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()
2992 pll_state->mg_pll_div1 = in icl_calc_mg_pll_state()
3078 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3435 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3508 hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3509 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3678 intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3733 val |= hw_state->mg_pll_div1; in dkl_pll_write()
3964 hw_state->mg_pll_div1, in icl_dump_hw_state()
H A Dintel_display_debugfs.c678 seq_printf(m, " mg_pll_div1: 0x%08x\n", in i915_shared_dplls_info()
679 pll->state.hw_state.mg_pll_div1); in i915_shared_dplls_info()
H A Dintel_display.c5342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); in intel_pipe_config_compare()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h205 u32 mg_pll_div1; member
H A Dintel_dpll_mgr.c3303 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()
3324 pll_state->mg_pll_div1 = in icl_calc_mg_pll_state()
3410 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3712 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3788 hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3789 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3938 intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
4001 val |= hw_state->mg_pll_div1; in dkl_pll_write()
4221 hw_state->mg_pll_div1, in icl_dump_hw_state()
H A Dintel_display_debugfs.c952 seq_printf(m, " mg_pll_div1: 0x%08x\n", in i915_shared_dplls_info()
953 pll->state.hw_state.mg_pll_div1); in i915_shared_dplls_info()
H A Dintel_display.c14014 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); in intel_pipe_config_compare()

Completed in 48 milliseconds