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Searched refs:mask2 (Results 1 - 25 of 116) sorted by relevance

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/kernel/linux/linux-6.6/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c27 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
33 mask2 = create_cpumask(); in create_cpumask_set()
34 if (!mask2) { in create_cpumask_set()
43 bpf_cpumask_release(mask2); in create_cpumask_set()
51 bpf_cpumask_release(mask2); in create_cpumask_set()
58 *out2 = mask2; in create_cpumask_set()
181 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
191 mask2 = create_cpumask(); in BPF_PROG()
192 if (!mask2) in BPF_PROG()
196 bpf_cpumask_set_cpu(1, mask2); in BPF_PROG()
245 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
292 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
334 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
467 struct bpf_cpumask *mask1, *mask2; BPF_PROG() local
[all...]
/kernel/linux/linux-5.10/drivers/soc/fsl/qe/
H A Dgpio.c249 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
256 qe_clrsetbits_be32(&regs->cpdir2, mask2, in qe_pin_set_dedicated()
257 sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
258 qe_clrsetbits_be32(&regs->cppar2, mask2, in qe_pin_set_dedicated()
259 sregs->cppar2 & mask2); in qe_pin_set_dedicated()
261 qe_clrsetbits_be32(&regs->cpdir1, mask2, in qe_pin_set_dedicated()
262 sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
263 qe_clrsetbits_be32(&regs->cppar1, mask2, in qe_pin_set_dedicated()
264 sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/kernel/linux/linux-6.6/drivers/soc/fsl/qe/
H A Dgpio.c242 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
249 qe_clrsetbits_be32(&regs->cpdir2, mask2, in qe_pin_set_dedicated()
250 sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
251 qe_clrsetbits_be32(&regs->cppar2, mask2, in qe_pin_set_dedicated()
252 sregs->cppar2 & mask2); in qe_pin_set_dedicated()
254 qe_clrsetbits_be32(&regs->cpdir1, mask2, in qe_pin_set_dedicated()
255 sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
256 qe_clrsetbits_be32(&regs->cppar1, mask2, in qe_pin_set_dedicated()
257 sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/kernel/linux/linux-5.10/fs/orangefs/
H A Dorangefs-debugfs.c64 __u64 mask2; member
457 c_mask.mask2); in orangefs_debug_write()
544 (unsigned long long *)&(cdm_array[i].mask2)); in orangefs_prepare_cdm_array()
756 (mask->mask2 & cdm_array[index].mask2)) { in do_c_string()
800 (c_mask->mask2 == cdm_array[client_all_index].mask2)) { in check_amalgam_keyword()
807 (c_mask->mask2 == cdm_array[client_verbose_index].mask2)) { in check_amalgam_keyword()
876 (**sane_mask).mask2 in do_c_mask()
[all...]
/kernel/linux/linux-6.6/fs/orangefs/
H A Dorangefs-debugfs.c64 __u64 mask2; member
457 c_mask.mask2); in orangefs_debug_write()
544 (unsigned long long *)&(cdm_array[i].mask2)); in orangefs_prepare_cdm_array()
756 (mask->mask2 & cdm_array[index].mask2)) { in do_c_string()
800 (c_mask->mask2 == cdm_array[client_all_index].mask2)) { in check_amalgam_keyword()
807 (c_mask->mask2 == cdm_array[client_verbose_index].mask2)) { in check_amalgam_keyword()
876 (**sane_mask).mask2 in do_c_mask()
[all...]
/kernel/linux/linux-5.10/arch/mips/sgi-ip22/
H A Dip22-int.c114 u8 mask2; in indy_local0_irqdispatch() local
118 mask2 = sgint->vmeistat & sgint->cmeimask0; in indy_local0_irqdispatch()
119 irq = lc2msk_to_irqnr[mask2]; in indy_local0_irqdispatch()
136 u8 mask2; in indy_local1_irqdispatch() local
140 mask2 = sgint->vmeistat & sgint->cmeimask1; in indy_local1_irqdispatch()
141 irq = lc3msk_to_irqnr[mask2]; in indy_local1_irqdispatch()
/kernel/linux/linux-6.6/arch/mips/sgi-ip22/
H A Dip22-int.c114 u8 mask2; in indy_local0_irqdispatch() local
118 mask2 = sgint->vmeistat & sgint->cmeimask0; in indy_local0_irqdispatch()
119 irq = lc2msk_to_irqnr[mask2]; in indy_local0_irqdispatch()
136 u8 mask2; in indy_local1_irqdispatch() local
140 mask2 = sgint->vmeistat & sgint->cmeimask1; in indy_local1_irqdispatch()
141 irq = lc3msk_to_irqnr[mask2]; in indy_local1_irqdispatch()
/kernel/linux/linux-5.10/sound/pci/ice1712/
H A Dwm8776.c140 .mask2 = WM8776_DACVOL_MASK,
150 .mask2 = WM8776_DAC_PL_RR,
166 .mask2 = WM8776_HPVOL_MASK,
184 .mask2 = WM8776_VOL_HPZCEN,
211 .mask2 = WM8776_PHASE_INVERTR,
227 .mask2 = WM8776_ADC_GAIN_MASK,
237 .mask2 = WM8776_ADC_MUTER,
492 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8776_ctl_get()
493 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8776_ctl_get()
532 val &= ~wm->ctl[n].mask2; in snd_wm8776_ctl_put()
[all...]
H A Dwm8766.c37 .mask2 = WM8766_VOL_MASK,
48 .mask2 = WM8766_VOL_MASK,
59 .mask2 = WM8766_VOL_MASK,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8766_ctl_get()
219 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_get()
258 val &= ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
259 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
266 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
/kernel/linux/linux-6.6/sound/pci/ice1712/
H A Dwm8776.c136 .mask2 = WM8776_DACVOL_MASK,
146 .mask2 = WM8776_DAC_PL_RR,
162 .mask2 = WM8776_HPVOL_MASK,
180 .mask2 = WM8776_VOL_HPZCEN,
207 .mask2 = WM8776_PHASE_INVERTR,
223 .mask2 = WM8776_ADC_GAIN_MASK,
233 .mask2 = WM8776_ADC_MUTER,
488 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8776_ctl_get()
489 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8776_ctl_get()
528 val &= ~wm->ctl[n].mask2; in snd_wm8776_ctl_put()
[all...]
H A Dwm8766.c37 .mask2 = WM8766_VOL_MASK,
48 .mask2 = WM8766_VOL_MASK,
59 .mask2 = WM8766_VOL_MASK,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8766_ctl_get()
219 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_get()
258 val &= ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
259 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
266 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
H A Dar9003_mac.c186 u32 mask2 = 0; in ar9003_hw_get_isr() local
216 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
218 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
220 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
222 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
224 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
226 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
228 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
230 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
302 *masked |= mask2; in ar9003_hw_get_isr()
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
H A Dar9003_mac.c187 u32 mask2 = 0; in ar9003_hw_get_isr() local
217 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
219 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
221 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
223 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
225 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
227 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
229 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
231 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
303 *masked |= mask2; in ar9003_hw_get_isr()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c335 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2()
339 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
345 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3()
350 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
357 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4()
363 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
371 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5()
378 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
387 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6()
395 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift in generic_reg_get6()
333 generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2) generic_reg_get2() argument
343 generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3) generic_reg_get3() argument
355 generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4) generic_reg_get4() argument
369 generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5) generic_reg_get5() argument
385 generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6) generic_reg_get6() argument
403 generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7) generic_reg_get7() argument
423 generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8) generic_reg_get8() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c290 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2()
294 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
300 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3()
305 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
312 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4()
318 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
326 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5()
333 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
342 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6()
350 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift in generic_reg_get6()
288 generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2) generic_reg_get2() argument
298 generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3) generic_reg_get3() argument
310 generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4) generic_reg_get4() argument
324 generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5) generic_reg_get5() argument
340 generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6) generic_reg_get6() argument
358 generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7) generic_reg_get7() argument
378 generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8) generic_reg_get8() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
244 reg2 ## __ ## mask2 ## _MASK,\
246 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
239 reg2 ## __ ## mask2 ## _MASK,\
241 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
239 reg2 ## __ ## mask2 ## _MASK,\
241 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
222 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
234 reg2 ## __ ## mask2 ## _MASK,\
236 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
232 reg2 ## __ ## mask2 ## _MASK,\
234 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
223 reg2 ## __ ## mask2 ## _MASK,\
225 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
233 reg2 ## __ ## mask2 ## _MASK,\
235 reg2 ## __ ## mask2 ## _MASK \
/kernel/linux/linux-5.10/fs/affs/
H A Dbitmap.c122 u32 blk, bmap, bit, mask, mask2, tmp; in affs_alloc_block() local
208 mask2 = mask = 1 << (bit & 31); in affs_alloc_block()
212 while ((mask2 <<= 1)) { in affs_alloc_block()
213 if (!(tmp & mask2)) in affs_alloc_block()
216 mask |= mask2; in affs_alloc_block()

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