H A D | df_v3_6.c | 361 uint32_t *lo_base_addr, in df_v3_6_pmc_get_addr() 370 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4; in df_v3_6_pmc_get_addr() 374 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo5 : smnPerfMonCtrLo5; in df_v3_6_pmc_get_addr() 378 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo6 : smnPerfMonCtrLo6; in df_v3_6_pmc_get_addr() 382 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo7 : smnPerfMonCtrLo7; in df_v3_6_pmc_get_addr() 394 uint32_t *lo_base_addr, in df_v3_6_pmc_get_read_settings() 397 df_v3_6_pmc_get_addr(adev, config, counter_idx, 0, lo_base_addr, in df_v3_6_pmc_get_read_settings() 405 uint32_t *lo_base_addr, in df_v3_6_pmc_get_ctrl_settings() 415 df_v3_6_pmc_get_addr(adev, config, counter_idx, 1, lo_base_addr, in df_v3_6_pmc_get_ctrl_settings() 418 if ((*lo_base_addr in df_v3_6_pmc_get_ctrl_settings() 357 df_v3_6_pmc_get_addr(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_ctrl, uint32_t *lo_base_addr, uint32_t *hi_base_addr) df_v3_6_pmc_get_addr() argument 391 df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint32_t *lo_base_addr, uint32_t *hi_base_addr) df_v3_6_pmc_get_read_settings() argument 402 df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint32_t *lo_base_addr, uint32_t *hi_base_addr, uint32_t *lo_val, uint32_t *hi_val, bool is_enable) df_v3_6_pmc_get_ctrl_settings() argument 502 uint32_t lo_base_addr = 0, hi_base_addr = 0; df_v3_6_reset_perfmon_cntr() local 517 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; df_v3_6_pmc_start() local 559 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; df_v3_6_pmc_stop() local 598 uint32_t lo_base_addr = 0, hi_base_addr = 0, lo_val = 0, hi_val = 0; df_v3_6_pmc_get_count() local [all...] |