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Searched refs:link_width_cntl (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dr300.c504 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
541 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
545 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
549 link_width_cntl |= mask; in rv370_set_pcie_lanes()
550 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
551 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
555 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
556 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
557 link_width_cntl in rv370_set_pcie_lanes()
563 u32 link_width_cntl; rv370_get_pcie_lanes() local
[all...]
H A Drv770.c2027 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2050 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2051 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2052 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2053 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2054 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2055 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2056 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2058 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2060 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
[all...]
H A Dr600.c4404 u32 link_width_cntl, mask; in r600_set_pcie_lanes() local
4446 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_set_pcie_lanes()
4447 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; in r600_set_pcie_lanes()
4448 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; in r600_set_pcie_lanes()
4449 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | in r600_set_pcie_lanes()
4452 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in r600_set_pcie_lanes()
4457 u32 link_width_cntl; in r600_get_pcie_lanes() local
4471 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_get_pcie_lanes()
4473 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { in r600_get_pcie_lanes()
4494 u32 link_width_cntl, lane in r600_pcie_gen2_enable() local
[all...]
H A Devergreen.c5329 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5359 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5360 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5361 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
5380 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5383 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5385 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5386 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dr300.c501 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
536 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
538 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
542 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
546 link_width_cntl |= mask; in rv370_set_pcie_lanes()
547 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
548 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
552 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
553 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
554 link_width_cntl in rv370_set_pcie_lanes()
560 u32 link_width_cntl; rv370_get_pcie_lanes() local
[all...]
H A Drv770.c2022 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2045 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2046 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2047 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2048 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2049 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2050 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2051 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2053 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2055 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
[all...]
H A Dr600.c4397 u32 link_width_cntl, mask; in r600_set_pcie_lanes() local
4439 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_set_pcie_lanes()
4440 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; in r600_set_pcie_lanes()
4441 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; in r600_set_pcie_lanes()
4442 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | in r600_set_pcie_lanes()
4445 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in r600_set_pcie_lanes()
4450 u32 link_width_cntl; in r600_get_pcie_lanes() local
4464 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_get_pcie_lanes()
4466 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { in r600_get_pcie_lanes()
4487 u32 link_width_cntl, lane in r600_pcie_gen2_enable() local
[all...]
H A Devergreen.c5328 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5358 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5359 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5360 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
5379 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5382 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5384 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5385 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1401 u32 link_width_cntl; in si_get_pcie_lanes() local
1406 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_get_pcie_lanes()
1408 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes()
1426 u32 link_width_cntl, mask; in si_set_pcie_lanes() local
1455 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_set_pcie_lanes()
1456 link_width_cntl &= ~LC_LINK_WIDTH_MASK; in si_set_pcie_lanes()
1457 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; in si_set_pcie_lanes()
1458 link_width_cntl |= (LC_RECONFIG_NOW | in si_set_pcie_lanes()
1461 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in si_set_pcie_lanes()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1517 u32 link_width_cntl; in si_get_pcie_lanes() local
1522 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_get_pcie_lanes()
1524 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes()
1542 u32 link_width_cntl, mask; in si_set_pcie_lanes() local
1571 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_set_pcie_lanes()
1572 link_width_cntl &= ~LC_LINK_WIDTH_MASK; in si_set_pcie_lanes()
1573 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; in si_set_pcie_lanes()
1574 link_width_cntl |= (LC_RECONFIG_NOW | in si_set_pcie_lanes()
1577 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in si_set_pcie_lanes()

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