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Searched refs:intf_cfg (Results 1 - 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_ctl.c508 u32 intf_cfg = 0; in dpu_hw_ctl_intf_cfg() local
510 intf_cfg |= (cfg->intf & 0xF) << 4; in dpu_hw_ctl_intf_cfg()
513 intf_cfg |= BIT(19); in dpu_hw_ctl_intf_cfg()
514 intf_cfg |= (cfg->mode_3d - 0x1) << 20; in dpu_hw_ctl_intf_cfg()
519 intf_cfg &= ~BIT(17); in dpu_hw_ctl_intf_cfg()
520 intf_cfg &= ~(0x3 << 15); in dpu_hw_ctl_intf_cfg()
523 intf_cfg |= BIT(17); in dpu_hw_ctl_intf_cfg()
524 intf_cfg |= ((cfg->stream_sel & 0x3) << 15); in dpu_hw_ctl_intf_cfg()
531 DPU_REG_WRITE(c, CTL_TOP, intf_cfg); in dpu_hw_ctl_intf_cfg()
H A Ddpu_hw_intf.c91 u32 intf_cfg; in dpu_hw_intf_setup_timing_engine() local
94 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
126 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */ in dpu_hw_intf_setup_timing_engine()
132 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */ in dpu_hw_intf_setup_timing_engine()
192 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
H A Ddpu_encoder_phys_vid.c247 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_phys_vid_setup_timing_engine() local
281 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_phys_vid_setup_timing_engine()
282 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; in dpu_encoder_phys_vid_setup_timing_engine()
283 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_phys_vid_setup_timing_engine()
284 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
289 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
H A Ddpu_encoder_phys_cmd.c58 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in _dpu_encoder_phys_cmd_update_intf_cfg() local
64 intf_cfg.intf = phys_enc->intf_idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
65 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; in _dpu_encoder_phys_cmd_update_intf_cfg()
66 intf_cfg.stream_sel = cmd_enc->stream_sel; in _dpu_encoder_phys_cmd_update_intf_cfg()
67 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
68 ctl->ops.setup_intf_cfg(ctl, &intf_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_ctl.c549 u32 intf_cfg = 0; in dpu_hw_ctl_intf_cfg() local
551 intf_cfg |= (cfg->intf & 0xF) << 4; in dpu_hw_ctl_intf_cfg()
554 intf_cfg |= BIT(19); in dpu_hw_ctl_intf_cfg()
555 intf_cfg |= (cfg->mode_3d - 0x1) << 20; in dpu_hw_ctl_intf_cfg()
559 intf_cfg |= (cfg->wb & 0x3) + 2; in dpu_hw_ctl_intf_cfg()
563 intf_cfg &= ~BIT(17); in dpu_hw_ctl_intf_cfg()
564 intf_cfg &= ~(0x3 << 15); in dpu_hw_ctl_intf_cfg()
567 intf_cfg |= BIT(17); in dpu_hw_ctl_intf_cfg()
568 intf_cfg |= ((cfg->stream_sel & 0x3) << 15); in dpu_hw_ctl_intf_cfg()
575 DPU_REG_WRITE(c, CTL_TOP, intf_cfg); in dpu_hw_ctl_intf_cfg()
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H A Ddpu_encoder_phys_wb.c195 struct dpu_hw_intf_cfg intf_cfg = {0}; in dpu_encoder_phys_wb_setup_cdp() local
201 intf_cfg.intf = DPU_NONE; in dpu_encoder_phys_wb_setup_cdp()
202 intf_cfg.wb = hw_wb->idx; in dpu_encoder_phys_wb_setup_cdp()
205 intf_cfg.merge_3d = hw_pp->merge_3d->idx; in dpu_encoder_phys_wb_setup_cdp()
216 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_cdp()
218 struct dpu_hw_intf_cfg intf_cfg = {0}; in dpu_encoder_phys_wb_setup_cdp() local
220 intf_cfg.intf = DPU_NONE; in dpu_encoder_phys_wb_setup_cdp()
221 intf_cfg.wb = hw_wb->idx; in dpu_encoder_phys_wb_setup_cdp()
222 intf_cfg.mode_3d = in dpu_encoder_phys_wb_setup_cdp()
224 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_cdp()
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H A Ddpu_encoder_phys_vid.c239 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_phys_vid_setup_timing_engine() local
276 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_phys_vid_setup_timing_engine()
277 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; in dpu_encoder_phys_vid_setup_timing_engine()
278 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_phys_vid_setup_timing_engine()
279 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
280 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
282 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
287 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
296 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); in dpu_encoder_phys_vid_setup_timing_engine()
H A Ddpu_encoder_phys_cmd.c52 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in _dpu_encoder_phys_cmd_update_intf_cfg() local
59 intf_cfg.intf = phys_enc->hw_intf->idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
60 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; in _dpu_encoder_phys_cmd_update_intf_cfg()
61 intf_cfg.stream_sel = cmd_enc->stream_sel; in _dpu_encoder_phys_cmd_update_intf_cfg()
62 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
63 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
64 ctl->ops.setup_intf_cfg(ctl, &intf_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
72 if (intf_cfg.dsc != 0) in _dpu_encoder_phys_cmd_update_intf_cfg()
H A Ddpu_hw_intf.c111 u32 intf_cfg, intf_cfg2 = 0; in dpu_hw_intf_setup_timing_engine() local
117 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
153 intf_cfg |= INTF_CFG_ACTIVE_H_EN; in dpu_hw_intf_setup_timing_engine()
159 intf_cfg |= INTF_CFG_ACTIVE_V_EN; in dpu_hw_intf_setup_timing_engine()
187 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; in dpu_hw_intf_setup_timing_engine()
222 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
H A Ddpu_encoder.c2037 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_helper_phys_cleanup() local
2088 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_helper_phys_cleanup()
2089 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_helper_phys_cleanup()
2090 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_helper_phys_cleanup()
2093 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_helper_phys_cleanup()
2095 intf_cfg.wb = phys_enc->hw_wb->idx; in dpu_encoder_helper_phys_cleanup()
2098 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_helper_phys_cleanup()
2101 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); in dpu_encoder_helper_phys_cleanup()
/kernel/linux/linux-6.6/sound/soc/qcom/qdsp6/
H A Daudioreach.c595 struct apm_display_port_module_intf_cfg *intf_cfg; in audioreach_display_port_set_media_format() local
639 intf_cfg = p; in audioreach_display_port_set_media_format()
640 param_data = &intf_cfg->param_data; in audioreach_display_port_set_media_format()
646 intf_cfg->cfg.channel_allocation = cfg->channel_allocation; in audioreach_display_port_set_media_format()
647 intf_cfg->cfg.mst_idx = 0; in audioreach_display_port_set_media_format()
648 intf_cfg->cfg.dptx_idx = cfg->dp_idx; in audioreach_display_port_set_media_format()
662 struct apm_codec_dma_module_intf_cfg *intf_cfg; in audioreach_codec_dma_set_media_format() local
708 intf_cfg = p; in audioreach_codec_dma_set_media_format()
709 param_data = &intf_cfg->param_data; in audioreach_codec_dma_set_media_format()
715 intf_cfg in audioreach_codec_dma_set_media_format()
944 struct apm_i2s_module_intf_cfg *intf_cfg; audioreach_i2s_set_media_format() local
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