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Searched refs:input_rate (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk-pll.c24 unsigned long input_rate; member
73 rate = pll->input_rate; in mmp_clk_pll_recalc_rate()
104 unsigned long input_rate, in mmp_clk_register_pll()
127 pll->input_rate = input_rate; in mmp_clk_register_pll()
159 clks[i].input_rate, in mmp_register_pll_clks()
100 mmp_clk_register_pll(char *name, unsigned long default_rate, void __iomem *enable_reg, u32 enable, void __iomem *reg, u8 shift, unsigned long input_rate, void __iomem *postdiv_reg, u8 postdiv_shift) mmp_clk_register_pll() argument
H A Dclk.h235 unsigned long input_rate; member
/kernel/linux/linux-6.6/drivers/clk/mmp/
H A Dclk-pll.c24 unsigned long input_rate; member
73 rate = pll->input_rate; in mmp_clk_pll_recalc_rate()
104 unsigned long input_rate, in mmp_clk_register_pll()
127 pll->input_rate = input_rate; in mmp_clk_register_pll()
159 clks[i].input_rate, in mmp_register_pll_clks()
100 mmp_clk_register_pll(char *name, unsigned long default_rate, void __iomem *enable_reg, u32 enable, void __iomem *reg, u8 shift, unsigned long input_rate, void __iomem *postdiv_reg, u8 postdiv_shift) mmp_clk_register_pll() argument
H A Dclk.h235 unsigned long input_rate; member
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-pll.c526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
956 unsigned long input_rate; in clk_plle_enable() local
963 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in clk_plle_enable()
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
1119 unsigned long flags = 0, input_rate; in clk_pllu_enable() local
1129 input_rate in clk_pllu_enable()
1251 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) tegra_pll_get_fixed_mdiv() argument
1449 _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, unsigned long input_rate, u32 n) _pllcx_update_dynamic_coef() argument
1613 unsigned long input_rate; clk_plle_tegra114_enable() local
1742 unsigned long flags = 0, input_rate; clk_pllu_tegra114_enable() local
2452 unsigned long input_rate; clk_plle_tegra210_enable() local
[all...]
H A Dclk-tegra210.c1060 unsigned long input_rate; in pllx_get_dyn_steps() local
1064 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()
1066 input_rate = 38400000; in pllx_get_dyn_steps()
1068 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1070 switch (input_rate) { in pllx_get_dyn_steps()
1087 __func__, input_rate); in pllx_get_dyn_steps()
1413 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1429 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg()
1450 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()
1427 tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long input_rate) tegra210_pll_fixed_mdiv_cfg() argument
[all...]
H A Dclk.h156 * @input_rate: input rate from source
165 unsigned long input_rate; member
905 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-pll.c526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
959 unsigned long input_rate; in clk_plle_enable() local
966 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in clk_plle_enable()
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
1122 unsigned long flags = 0, input_rate; in clk_pllu_enable() local
1132 input_rate in clk_pllu_enable()
1254 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) tegra_pll_get_fixed_mdiv() argument
1452 _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, unsigned long input_rate, u32 n) _pllcx_update_dynamic_coef() argument
1616 unsigned long input_rate; clk_plle_tegra114_enable() local
1745 unsigned long flags = 0, input_rate; clk_pllu_tegra114_enable() local
2455 unsigned long input_rate; clk_plle_tegra210_enable() local
[all...]
H A Dclk-tegra210.c1111 unsigned long input_rate; in pllx_get_dyn_steps() local
1115 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()
1117 input_rate = 38400000; in pllx_get_dyn_steps()
1119 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1121 switch (input_rate) { in pllx_get_dyn_steps()
1138 __func__, input_rate); in pllx_get_dyn_steps()
1464 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1480 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg()
1501 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()
1478 tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long input_rate) tegra210_pll_fixed_mdiv_cfg() argument
[all...]
H A Dclk.h156 * @input_rate: input rate from source
165 unsigned long input_rate; member
907 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
/kernel/linux/linux-5.10/sound/pci/ctxfi/
H A Dctatc.c195 atc_get_pitch(unsigned int input_rate, unsigned int output_rate) in atc_get_pitch() argument
201 pitch = (input_rate / output_rate) << 24; in atc_get_pitch()
202 input_rate %= output_rate; in atc_get_pitch()
203 input_rate /= 100; in atc_get_pitch()
205 for (b = 31; ((b >= 0) && !(input_rate >> b)); ) in atc_get_pitch()
209 input_rate <<= (31 - b); in atc_get_pitch()
210 input_rate /= output_rate; in atc_get_pitch()
213 input_rate <<= b; in atc_get_pitch()
215 input_rate >>= -b; in atc_get_pitch()
217 pitch |= input_rate; in atc_get_pitch()
[all...]
/kernel/linux/linux-6.6/sound/pci/ctxfi/
H A Dctatc.c195 atc_get_pitch(unsigned int input_rate, unsigned int output_rate) in atc_get_pitch() argument
201 pitch = (input_rate / output_rate) << 24; in atc_get_pitch()
202 input_rate %= output_rate; in atc_get_pitch()
203 input_rate /= 100; in atc_get_pitch()
205 for (b = 31; ((b >= 0) && !(input_rate >> b)); ) in atc_get_pitch()
209 input_rate <<= (31 - b); in atc_get_pitch()
210 input_rate /= output_rate; in atc_get_pitch()
213 input_rate <<= b; in atc_get_pitch()
215 input_rate >>= -b; in atc_get_pitch()
217 pitch |= input_rate; in atc_get_pitch()
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/kernel/linux/linux-5.10/arch/c6x/include/asm/
H A Dclock.h109 u32 input_rate; member
/kernel/linux/linux-5.10/arch/c6x/platforms/
H A Dpll.c224 rate = pll->input_rate; in clk_sysclk_recalc()
276 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
/kernel/linux/linux-5.10/sound/soc/stm/
H A Dstm32_sai_sub.c315 unsigned long input_rate, in stm32_sai_get_clk_div()
321 div = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_sai_get_clk_div()
328 if (input_rate % div) in stm32_sai_get_clk_div()
331 output_rate, input_rate / div); in stm32_sai_get_clk_div()
314 stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, unsigned long input_rate, unsigned long output_rate) stm32_sai_get_clk_div() argument
/kernel/linux/linux-6.6/sound/soc/stm/
H A Dstm32_sai_sub.c313 unsigned long input_rate, in stm32_sai_get_clk_div()
319 div = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_sai_get_clk_div()
326 if (input_rate % div) in stm32_sai_get_clk_div()
329 output_rate, input_rate / div); in stm32_sai_get_clk_div()
312 stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, unsigned long input_rate, unsigned long output_rate) stm32_sai_get_clk_div() argument
H A Dstm32_i2s.c265 unsigned long input_rate, in stm32_i2s_calc_clk_div()
271 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_i2s_calc_clk_div()
292 if (input_rate % divider) in stm32_i2s_calc_clk_div()
295 output_rate, input_rate / divider); in stm32_i2s_calc_clk_div()
264 stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s, unsigned long input_rate, unsigned long output_rate) stm32_i2s_calc_clk_div() argument

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