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Help
Searched
refs:input_clks
(Results
1 - 2
of
2
) sorted by relevance
/kernel/linux/linux-6.6/drivers/phy/cadence/
H
A
D
phy-cadence-sierra.c
401
struct clk *
input_clks
[CDNS_SIERRA_INPUT_CLOCKS];
member
556
clk_set_rate(phy->
input_clks
[CMN_REFCLK_DIG_DIV], 25000000);
in cdns_sierra_phy_init()
557
clk_set_rate(phy->
input_clks
[CMN_REFCLK1_DIG_DIV], 25000000);
in cdns_sierra_phy_init()
1162
sp->
input_clks
[CMN_REFCLK_DIG_DIV] = clk;
in cdns_sierra_phy_get_clocks()
1170
sp->
input_clks
[CMN_REFCLK1_DIG_DIV] = clk;
in cdns_sierra_phy_get_clocks()
1186
sp->
input_clks
[PHY_CLK] = clk;
in cdns_sierra_phy_clk()
1188
ret = clk_prepare_enable(sp->
input_clks
[PHY_CLK]);
in cdns_sierra_phy_clk()
1220
clk_disable_unprepare(sp->
input_clks
[PHY_CLK]);
in cdns_sierra_phy_disable_clocks()
1262
clk_set_rate(sp->
input_clks
[CMN_REFCLK_DIG_DIV], 25000000);
in cdns_sierra_phy_configure_multilink()
1263
clk_set_rate(sp->
input_clks
[CMN_REFCLK1_DIG_DI
in cdns_sierra_phy_configure_multilink()
[all...]
/kernel/linux/linux-6.6/drivers/phy/ti/
H
A
D
phy-j721e-wiz.c
392
struct clk *
input_clks
[WIZ_MAX_INPUT_CLOCKS];
member
832
clk = wiz->
input_clks
[mux_sel->parents[i]];
in wiz_mux_clk_register()
1096
wiz->
input_clks
[WIZ_CORE_REFCLK] = clk;
in wiz_clock_init()
1130
wiz->
input_clks
[WIZ_CORE_REFCLK1] = clk;
in wiz_clock_init()
1145
wiz->
input_clks
[WIZ_EXT_REFCLK] = clk;
in wiz_clock_init()
Completed in 6 milliseconds