Home
last modified time | relevance | path

Searched refs:imx_clk_pllv2 (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx5.c288 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx50_clocks_init()
292 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx50_clocks_init()
296 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx50_clocks_init()
373 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx51_clocks_init()
377 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx51_clocks_init()
381 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx51_clocks_init()
479 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx53_clocks_init()
483 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx53_clocks_init()
487 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx53_clocks_init()
491 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_s in mx53_clocks_init()
[all...]
H A Dclk.h126 #define imx_clk_pllv2(name, parent, base) \ macro
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx5.c288 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx50_clocks_init()
292 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx50_clocks_init()
296 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx50_clocks_init()
373 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx51_clocks_init()
377 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx51_clocks_init()
381 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx51_clocks_init()
479 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx53_clocks_init()
483 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx53_clocks_init()
487 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx53_clocks_init()
491 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_s in mx53_clocks_init()
[all...]
H A Dclk.h160 #define imx_clk_pllv2(name, parent, base) \ macro

Completed in 4 milliseconds