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Searched refs:idx_value (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dr200.c157 u32 idx_value; in r200_packet0_check() local
161 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
189 track->zb.offset = idx_value; in r200_packet0_check()
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
202 track->cb[0].offset = idx_value; in r200_packet0_check()
204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
226 tmp = idx_value & ~(0x7 << 2); in r200_packet0_check()
230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
273 track->textures[i].cube_info[face - 1].offset = idx_value; in r200_packet0_check()
274 ib[idx] = idx_value in r200_packet0_check()
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H A Dr300.c641 u32 idx_value; in r300_packet0_check() local
645 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
677 track->cb[i].offset = idx_value; in r300_packet0_check()
679 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
690 track->zb.offset = idx_value; in r300_packet0_check()
692 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
720 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()
721 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()
730 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
740 track->vap_vf_cntl = idx_value; in r300_packet0_check()
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H A Dr600_cs.c1634 u32 idx_value; in r600_packet3_check() local
1639 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1672 (idx_value & 0xfffffff0) + in r600_packet3_check()
1713 idx_value + in r600_packet3_check()
1755 if (idx_value & 0x10) { in r600_packet3_check()
1770 } else if (idx_value & 0x100) { in r600_packet3_check()
1907 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()
1923 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()
1943 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()
2023 start_reg = (idx_value << in r600_packet3_check()
2380 u32 idx, idx_value; r600_dma_cs_parse() local
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H A Dr100.c1310 u32 idx_value; in r100_packet3_load_vbpntr() local
1330 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1333 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1345 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1356 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1359 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1562 u32 idx_value; in r100_packet0_check() local
1567 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1596 track->zb.offset = idx_value; in r100_packet0_check()
1598 ib[idx] = idx_value in r100_packet0_check()
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H A Devergreen_cs.c1782 u32 idx_value; in evergreen_packet3_check() local
1787 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1820 (idx_value & 0xfffffff0) + in evergreen_packet3_check()
1866 idx_value + in evergreen_packet3_check()
1901 idx_value + in evergreen_packet3_check()
2012 if (idx_value != 1) { in evergreen_packet3_check()
2045 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2047 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2079 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2092 if (idx_value in evergreen_packet3_check()
3352 u32 idx_value = ib[idx]; evergreen_vm_packet3_check() local
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H A Dsi.c4488 u32 idx_value = ib[idx]; in si_vm_packet3_cp_dma_check() local
4492 start_reg = idx_value << 2; in si_vm_packet3_cp_dma_check()
4539 u32 idx_value = ib[idx]; in si_vm_packet3_gfx_check() local
4590 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4597 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4599 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()
4612 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()
4619 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()
4626 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()
4657 u32 idx_value in si_vm_packet3_compute_check() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dr200.c157 u32 idx_value; in r200_packet0_check() local
161 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
189 track->zb.offset = idx_value; in r200_packet0_check()
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
202 track->cb[0].offset = idx_value; in r200_packet0_check()
204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
226 tmp = idx_value & ~(0x7 << 2); in r200_packet0_check()
230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
273 track->textures[i].cube_info[face - 1].offset = idx_value; in r200_packet0_check()
274 ib[idx] = idx_value in r200_packet0_check()
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H A Dr300.c635 u32 idx_value; in r300_packet0_check() local
639 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
671 track->cb[i].offset = idx_value; in r300_packet0_check()
673 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
684 track->zb.offset = idx_value; in r300_packet0_check()
686 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
714 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()
715 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()
724 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
734 track->vap_vf_cntl = idx_value; in r300_packet0_check()
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H A Dr600_cs.c1636 u32 idx_value; in r600_packet3_check() local
1641 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1674 (idx_value & 0xfffffff0) + in r600_packet3_check()
1715 idx_value + in r600_packet3_check()
1757 if (idx_value & 0x10) { in r600_packet3_check()
1772 } else if (idx_value & 0x100) { in r600_packet3_check()
1909 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()
1925 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()
1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()
2025 start_reg = (idx_value << in r600_packet3_check()
2382 u32 idx, idx_value; r600_dma_cs_parse() local
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H A Dr100.c1318 u32 idx_value; in r100_packet3_load_vbpntr() local
1338 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1341 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1353 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1364 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1367 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1570 u32 idx_value; in r100_packet0_check() local
1575 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1604 track->zb.offset = idx_value; in r100_packet0_check()
1606 ib[idx] = idx_value in r100_packet0_check()
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H A Devergreen_cs.c1781 u32 idx_value; in evergreen_packet3_check() local
1786 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1819 (idx_value & 0xfffffff0) + in evergreen_packet3_check()
1865 idx_value + in evergreen_packet3_check()
1900 idx_value + in evergreen_packet3_check()
2011 if (idx_value != 1) { in evergreen_packet3_check()
2044 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2046 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2091 if (idx_value in evergreen_packet3_check()
3351 u32 idx_value = ib[idx]; evergreen_vm_packet3_check() local
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H A Dsi.c4483 u32 idx_value = ib[idx]; in si_vm_packet3_cp_dma_check() local
4487 start_reg = idx_value << 2; in si_vm_packet3_cp_dma_check()
4534 u32 idx_value = ib[idx]; in si_vm_packet3_gfx_check() local
4585 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4592 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4594 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()
4607 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()
4614 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()
4621 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()
4652 u32 idx_value in si_vm_packet3_compute_check() local
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