| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/ |
| H A D | mock_gtt.c | 30 enum i915_cache_level level, in mock_insert_page()
37 enum i915_cache_level level, u32 flags) in mock_insert_entries()
44 enum i915_cache_level cache_level, in mock_bind_ppgtt()
99 enum i915_cache_level cache_level, in mock_bind_ggtt()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_domain.h | 10 enum i915_cache_level;
13 enum i915_cache_level cache_level);
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| H A D | i915_gem_object_types.h | 122 * enum i915_cache_level - The supported GTT caching values for system memory
132 enum i915_cache_level { enum
373 * i915_cache_level since PAT indices are being used by both userspace
376 * i915_cache_level into pat index, for more details check the macros
379 * the entries of enum i915_cache_level for pre-GEN12 platforms (See
412 * GTT caching bits(see enum i915_cache_level). When enabling coherency
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| H A D | i915_gem_domain.c | 271 enum i915_cache_level cache_level) in i915_gem_object_set_cache_level()
345 enum i915_cache_level level; in i915_gem_set_caching_ioctl()
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| H A D | i915_gem_object.c | 49 enum i915_cache_level level) in i915_gem_get_pat_index()
58 enum i915_cache_level lvl) in i915_gem_object_has_cache_level()
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| H A D | i915_gem_object.h | 36 enum i915_cache_level level);
38 enum i915_cache_level lvl);
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| H A D | i915_gem_ttm_move.c | 51 static enum i915_cache_level
199 enum i915_cache_level src_level, dst_level; in i915_ttm_accel_move()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt.c | 180 enum i915_cache_level level, in gen8_ggtt_pte_encode()
194 enum i915_cache_level level, in gen8_ggtt_insert_page()
208 enum i915_cache_level level, in gen8_ggtt_insert_entries()
245 enum i915_cache_level level, in gen6_ggtt_insert_page()
265 enum i915_cache_level level, in gen6_ggtt_insert_entries()
335 enum i915_cache_level level;
351 enum i915_cache_level level, in bxt_vtd_ggtt_insert_page__BKL()
362 enum i915_cache_level level;
378 enum i915_cache_level level, in bxt_vtd_ggtt_insert_entries__BKL()
410 enum i915_cache_level cache_leve in i915_ggtt_insert_page()
[all...] |
| H A D | intel_gtt.h | 137 enum i915_cache_level;
195 enum i915_cache_level cache_level,
264 enum i915_cache_level level,
276 enum i915_cache_level cache_level,
280 enum i915_cache_level cache_level,
535 u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
559 enum i915_cache_level cache_level,
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| H A D | gen8_ppgtt.c | 17 const enum i915_cache_level level) in gen8_pde_encode()
30 enum i915_cache_level level, in gen8_pte_encode()
362 enum i915_cache_level cache_level, in gen8_ppgtt_insert_pte()
409 enum i915_cache_level cache_level, in gen8_ppgtt_insert_huge()
530 enum i915_cache_level cache_level, in gen8_ppgtt_insert()
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| H A D | intel_ppgtt.c | 99 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) in __set_pd_entry()
181 enum i915_cache_level cache_level, in ppgtt_bind_vma()
96 __set_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, struct i915_page_table * const to, u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) __set_pd_entry() argument
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| H A D | gen6_ppgtt.c | 118 enum i915_cache_level cache_level, in gen6_ppgtt_insert_entries()
304 enum i915_cache_level cache_level, in pd_vma_bind()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_domain.c | 192 enum i915_cache_level cache_level) in i915_gem_object_set_cache_level()
257 enum i915_cache_level level; in i915_gem_set_caching_ioctl()
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| H A D | i915_gem_client_blt.c | 38 enum i915_cache_level cache_level, in vma_bind()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_vma_types.h | 35 enum i915_cache_level;
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| H A D | i915_vma.h | 197 enum i915_cache_level cache_level,
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| H A D | i915_vma.c | 299 enum i915_cache_level cache_level;
377 enum i915_cache_level cache_level, in i915_vma_bind()
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| H A D | i915_drv.h | 348 enum i915_cache_level { enum
1889 enum i915_cache_level cache_level);
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ppgtt.c | 102 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) in __set_pd_entry()
99 __set_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, struct i915_page_table * const to, u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) __set_pd_entry() argument
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| H A D | intel_gtt.h | 638 u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
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| H A D | gen8_ppgtt.c | 19 const enum i915_cache_level level) in gen8_pde_encode()
42 * i915_cache_level, so the switch-case here is still valid. in gen8_pte_encode()
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