Home
last modified time | relevance | path

Searched refs:i1 (Results 1 - 25 of 95) sorted by relevance

1234

/kernel/linux/linux-5.10/arch/sparc/lib/
H A DNGmemcpy.S170 FUNC_NAME: /* %i0=dst, %i1=src, %i2=len */
179 or %o0, %i1, %i3
196 * %i1: src
203 LOAD(prefetch, %i1, #one_read)
213 EX_LD(LOAD(ldub, %i1, %g1), NG_ret_i2_plus_i4_plus_1)
215 add %i1, 1, %i1
234 andcc %i1, (16 - 1), %i4
241 sub %i1, %i4, %i1
[all...]
H A Dmemcpy.S303 ldub [%i1], %g5
304 add %i1, 1, %i1
310 ldub [%i1], %g3
311 add %i1, 2, %i1
314 ldub [%i1 - 1], %g3
318 and %i1, 3, %g2
320 and %i1, -4, %i1
[all...]
H A DNGpage.S24 prefetch [%i1 + 0x00], #one_read
25 prefetch [%i1 + 0x40], #one_read
27 1: prefetch [%i1 + 0x80], #one_read
28 prefetch [%i1 + 0xc0], #one_read
29 ldda [%i1 + 0x00] %asi, %o2
30 ldda [%i1 + 0x10] %asi, %o4
31 ldda [%i1 + 0x20] %asi, %l2
32 ldda [%i1 + 0x30] %asi, %l4
41 ldda [%i1 + 0x40] %asi, %o2
42 ldda [%i1
[all...]
/kernel/linux/linux-6.6/arch/sparc/lib/
H A DNGmemcpy.S169 FUNC_NAME: /* %i0=dst, %i1=src, %i2=len */
178 or %o0, %i1, %i3
195 * %i1: src
202 LOAD(prefetch, %i1, #one_read)
212 EX_LD(LOAD(ldub, %i1, %g1), NG_ret_i2_plus_i4_plus_1)
214 add %i1, 1, %i1
233 andcc %i1, (16 - 1), %i4
240 sub %i1, %i4, %i1
[all...]
H A Dmemcpy.S304 ldub [%i1], %g5
305 add %i1, 1, %i1
311 ldub [%i1], %g3
312 add %i1, 2, %i1
315 ldub [%i1 - 1], %g3
319 and %i1, 3, %g2
321 and %i1, -4, %i1
[all...]
H A DNGpage.S24 prefetch [%i1 + 0x00], #one_read
25 prefetch [%i1 + 0x40], #one_read
27 1: prefetch [%i1 + 0x80], #one_read
28 prefetch [%i1 + 0xc0], #one_read
29 ldda [%i1 + 0x00] %asi, %o2
30 ldda [%i1 + 0x10] %asi, %o4
31 ldda [%i1 + 0x20] %asi, %l2
32 ldda [%i1 + 0x30] %asi, %l4
41 ldda [%i1 + 0x40] %asi, %o2
42 ldda [%i1
[all...]
/kernel/linux/linux-5.10/arch/arm64/crypto/
H A Daes-ce.S57 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3, i4
60 .ifnb \i1
61 aes\de \i1\().16b, \k\().16b
62 aes\mc \i1\().16b, \i1\().16b
77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4
79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4
81 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3, \i4
86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4
88 .ifnb \i1
[all...]
/kernel/linux/linux-6.6/arch/arm64/crypto/
H A Daes-ce.S57 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3, i4
60 .ifnb \i1
61 aes\de \i1\().16b, \k\().16b
62 aes\mc \i1\().16b, \i1\().16b
77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4
79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4
81 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3, \i4
86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4
88 .ifnb \i1
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h353 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE() argument
355 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_OP() argument
375 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
377 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
379 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
381 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
383 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
385 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
397 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3() argument
399 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3_SEL() argument
415 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV() argument
417 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV_VAL() argument
419 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV() argument
421 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
423 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV() argument
425 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
427 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV() argument
429 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
431 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV() argument
433 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
439 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT() argument
441 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT_VAL() argument
570 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV() argument
572 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV_VAL() argument
574 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV() argument
576 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
578 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV() argument
580 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV_VAL() argument
582 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV() argument
584 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
586 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV() argument
588 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV_VAL() argument
821 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV() argument
823 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV_VAL() argument
825 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV() argument
827 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
829 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV() argument
831 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
833 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV() argument
835 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
837 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV() argument
839 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h360 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE() argument
362 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_OP() argument
382 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
384 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
386 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
388 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
390 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
392 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
404 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3() argument
406 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3_SEL() argument
422 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV() argument
424 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV_VAL() argument
426 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV() argument
428 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
430 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV() argument
432 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
434 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV() argument
436 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
438 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV() argument
440 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
446 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT() argument
448 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT_VAL() argument
577 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV() argument
579 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV_VAL() argument
581 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV() argument
583 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
585 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV() argument
587 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV_VAL() argument
589 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV() argument
591 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
593 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV() argument
595 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV_VAL() argument
828 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV() argument
830 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV_VAL() argument
832 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV() argument
834 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
836 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV() argument
838 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
840 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV() argument
842 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
844 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV() argument
846 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
[all...]
/kernel/linux/linux-5.10/arch/arm64/kvm/
H A Dsys_regs.h132 static inline int cmp_sys_reg(const struct sys_reg_desc *i1, in cmp_sys_reg() argument
135 BUG_ON(i1 == i2); in cmp_sys_reg()
136 if (!i1) in cmp_sys_reg()
140 if (i1->Op0 != i2->Op0) in cmp_sys_reg()
141 return i1->Op0 - i2->Op0; in cmp_sys_reg()
142 if (i1->Op1 != i2->Op1) in cmp_sys_reg()
143 return i1->Op1 - i2->Op1; in cmp_sys_reg()
144 if (i1->CRn != i2->CRn) in cmp_sys_reg()
145 return i1->CRn - i2->CRn; in cmp_sys_reg()
146 if (i1 in cmp_sys_reg()
[all...]
/kernel/linux/linux-6.6/arch/arm64/kvm/
H A Dsys_regs.h189 static inline int cmp_sys_reg(const struct sys_reg_desc *i1, in cmp_sys_reg() argument
192 BUG_ON(i1 == i2); in cmp_sys_reg()
193 if (!i1) in cmp_sys_reg()
197 if (i1->Op0 != i2->Op0) in cmp_sys_reg()
198 return i1->Op0 - i2->Op0; in cmp_sys_reg()
199 if (i1->Op1 != i2->Op1) in cmp_sys_reg()
200 return i1->Op1 - i2->Op1; in cmp_sys_reg()
201 if (i1->CRn != i2->CRn) in cmp_sys_reg()
202 return i1->CRn - i2->CRn; in cmp_sys_reg()
203 if (i1 in cmp_sys_reg()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5.xml.h321 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } in REG_MDP5_IGC_LUT() argument
323 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } in REG_MDP5_IGC_LUT_REG() argument
374 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } in REG_MDP5_CTL_LAYER() argument
376 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } in REG_MDP5_CTL_LAYER_REG() argument
509 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } in REG_MDP5_CTL_LAYER_EXT() argument
511 REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_EXT_REG() argument
641 REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
643 REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
657 REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
659 REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
673 REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
675 REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
683 REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
685 REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
943 REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT() argument
945 REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_LR() argument
971 REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_TB() argument
997 REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument
1118 REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND() argument
1120 REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_OP_MODE() argument
1142 REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_ALPHA() argument
1144 REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_ALPHA() argument
1146 REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
1148 REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
1150 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
1152 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1154 REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1156 REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1158 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1160 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1691 REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP() argument
1693 REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument
1707 REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument
1709 REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument
1723 REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS() argument
1725 REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument
1733 REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS() argument
1735 REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5.xml.h332 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } in REG_MDP5_IGC_LUT() argument
334 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } in REG_MDP5_IGC_LUT_REG() argument
385 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } in REG_MDP5_CTL_LAYER() argument
387 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } in REG_MDP5_CTL_LAYER_REG() argument
520 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } in REG_MDP5_CTL_LAYER_EXT() argument
522 REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_EXT_REG() argument
652 REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
654 REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
668 REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
670 REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
684 REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
686 REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
694 REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
696 REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
954 REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT() argument
956 REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_LR() argument
982 REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_TB() argument
1008 REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument
1129 REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND() argument
1131 REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_OP_MODE() argument
1153 REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_ALPHA() argument
1155 REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_ALPHA() argument
1157 REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
1159 REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
1161 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
1163 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1165 REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1167 REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1169 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1171 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1702 REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP() argument
1704 REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument
1718 REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument
1720 REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument
1734 REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS() argument
1736 REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument
1744 REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS() argument
1746 REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument
[all...]
/kernel/linux/linux-5.10/tools/testing/selftests/proc/
H A Dproc-uptime-001.c28 uint64_t start, u0, u1, i0, i1; in main() local
37 proc_uptime(fd, &u1, &i1); in main()
39 assert(i1 >= i0); in main()
41 i0 = i1; in main()
H A Dproc-uptime-002.c48 uint64_t u0, u1, i0, i1; in main() local
71 proc_uptime(fd, &u1, &i1); in main()
73 assert(i1 >= i0); in main()
75 i0 = i1; in main()
/kernel/linux/linux-5.10/drivers/isdn/mISDN/
H A Dl1oip_codec.c312 int i1, i2, c, sample; in l1oip_4bit_alloc() local
326 i1 = 0; in l1oip_4bit_alloc()
327 while (i1 < 256) { in l1oip_4bit_alloc()
329 c = ulaw_to_4bit[i1]; in l1oip_4bit_alloc()
331 c = alaw_to_4bit[i1]; in l1oip_4bit_alloc()
334 table_com[(i1 << 8) | i2] |= (c << 4); in l1oip_4bit_alloc()
335 table_com[(i2 << 8) | i1] |= c; in l1oip_4bit_alloc()
338 i1++; in l1oip_4bit_alloc()
342 i1 = 0; in l1oip_4bit_alloc()
343 while (i1 < 1 in l1oip_4bit_alloc()
[all...]
/kernel/linux/linux-6.6/drivers/isdn/mISDN/
H A Dl1oip_codec.c312 int i1, i2, c, sample; in l1oip_4bit_alloc() local
326 i1 = 0; in l1oip_4bit_alloc()
327 while (i1 < 256) { in l1oip_4bit_alloc()
329 c = ulaw_to_4bit[i1]; in l1oip_4bit_alloc()
331 c = alaw_to_4bit[i1]; in l1oip_4bit_alloc()
334 table_com[(i1 << 8) | i2] |= (c << 4); in l1oip_4bit_alloc()
335 table_com[(i2 << 8) | i1] |= c; in l1oip_4bit_alloc()
338 i1++; in l1oip_4bit_alloc()
342 i1 = 0; in l1oip_4bit_alloc()
343 while (i1 < 1 in l1oip_4bit_alloc()
[all...]
/kernel/linux/linux-5.10/arch/parisc/math-emu/
H A Dfpudispatch.c1166 struct { u_int i1; u_int i2; } ints; member
1193 &mtmp.ints.i1,&status))
1196 &atmp.ints.i1,&atmp.ints.i1,&status))
1201 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
1204 if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
1216 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
1219 if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
1229 fpregs[tm] = mtmp.ints.i1;
1231 fpregs[ta] = atmp.ints.i1;
1305 struct { u_int i1; u_int i2; } ints; global() member
[all...]
/kernel/linux/linux-6.6/arch/parisc/math-emu/
H A Dfpudispatch.c1166 struct { u_int i1; u_int i2; } ints; member
1193 &mtmp.ints.i1,&status))
1196 &atmp.ints.i1,&atmp.ints.i1,&status))
1201 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
1204 if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
1216 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,
1219 if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,
1229 fpregs[tm] = mtmp.ints.i1;
1231 fpregs[ta] = atmp.ints.i1;
1305 struct { u_int i1; u_int i2; } ints; global() member
[all...]
/kernel/linux/linux-5.10/arch/arm/kernel/
H A Dinsn.c10 unsigned long s, j1, j2, i1, i2, imm10, imm11; in __arm_gen_branch_thumb2() local
21 i1 = (offset >> 23) & 0x1; in __arm_gen_branch_thumb2()
26 j1 = (!i1) ^ s; in __arm_gen_branch_thumb2()
/kernel/linux/linux-6.6/arch/arm/kernel/
H A Dinsn.c10 unsigned long s, j1, j2, i1, i2, imm10, imm11; in __arm_gen_branch_thumb2() local
21 i1 = (offset >> 23) & 0x1; in __arm_gen_branch_thumb2()
26 j1 = (!i1) ^ s; in __arm_gen_branch_thumb2()
/kernel/linux/linux-5.10/include/sound/
H A Dpcm_params.h289 static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) in snd_interval_eq() argument
291 if (i1->empty) in snd_interval_eq()
294 return i1->empty; in snd_interval_eq()
295 return i1->min == i2->min && i1->openmin == i2->openmin && in snd_interval_eq()
296 i1->max == i2->max && i1->openmax == i2->openmax; in snd_interval_eq()
/kernel/linux/linux-6.6/include/sound/
H A Dpcm_params.h289 static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) in snd_interval_eq() argument
291 if (i1->empty) in snd_interval_eq()
294 return i1->empty; in snd_interval_eq()
295 return i1->min == i2->min && i1->openmin == i2->openmin && in snd_interval_eq()
296 i1->max == i2->max && i1->openmax == i2->openmax; in snd_interval_eq()
/kernel/linux/linux-5.10/drivers/video/fbdev/
H A Dc2p_core.h22 static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, in _transp() argument
25 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
27 d[i1] ^= t; in _transp()

Completed in 25 milliseconds

1234