| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| H A D | tidss_dispc.c | 321 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
323 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
328 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
330 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
402 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_GET() argument
405 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
408 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_FLD_MOD() argument
411 dispc_vid_write(dispc, hw_plane, idx, in VID_REG_FLD_MOD()
412 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), in VID_REG_FLD_MOD()
476 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane) in dispc_vid_irq_from_raw() argument
486 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane) dispc_vid_irq_to_raw() argument
512 dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) dispc_k2g_vid_read_irqstatus() argument
520 dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k2g_vid_write_irqstatus() argument
544 dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) dispc_k2g_vid_read_irqenable() argument
552 dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k2g_vid_set_irqenable() argument
627 dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) dispc_k3_vid_read_irqstatus() argument
635 dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k3_vid_write_irqstatus() argument
659 dispc_k3_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) dispc_k3_vid_read_irqenable() argument
667 dispc_k3_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k3_vid_set_irqenable() argument
1240 dispc_k2g_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_k2g_ovr_set_plane() argument
1249 dispc_am65x_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_am65x_ovr_set_plane() argument
1261 dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_j721e_ovr_set_plane() argument
1273 dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_ovr_set_plane() argument
1384 dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, const struct dispc_csc_coef *csc) dispc_k2g_vid_write_csc() argument
1407 dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, const struct dispc_csc_coef *csc) dispc_k3_vid_write_csc() argument
1504 dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state) dispc_vid_csc_setup() argument
1522 dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) dispc_vid_csc_enable() argument
1542 dispc_vid_write_fir_coefs(struct dispc_device *dispc, u32 hw_plane, enum dispc_vid_fir_coef_set coef_set, const struct tidss_scale_coefs *coefs) dispc_vid_write_fir_coefs() argument
1775 dispc_vid_set_scaling(struct dispc_device *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) dispc_vid_set_scaling() argument
1875 dispc_plane_set_pixel_format(struct dispc_device *dispc, u32 hw_plane, u32 fourcc) dispc_plane_set_pixel_format() argument
1914 dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) dispc_plane_check() argument
1985 dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) dispc_plane_setup() argument
2070 dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) dispc_plane_enable() argument
2077 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) dispc_vid_get_fifo_size() argument
2082 dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) dispc_vid_set_mflag_threshold() argument
2089 dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) dispc_vid_set_buf_threshold() argument
2098 unsigned int hw_plane; dispc_k2g_plane_init() local
2148 unsigned int hw_plane; dispc_k3_plane_init() local
[all...] |
| H A D | tidss_dispc.h | 95 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
123 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
126 int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
129 int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
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| H A D | tidss_plane.c | 29 u32 hw_plane = tplane->hw_plane_id; in tidss_plane_atomic_check() local
93 ret = dispc_plane_check(tidss->dispc, hw_plane, state, hw_videoport); in tidss_plane_atomic_check()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/tidss/ |
| H A D | tidss_dispc.c | 371 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
373 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
378 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
380 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
452 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_GET() argument
455 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
458 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_FLD_MOD() argument
461 dispc_vid_write(dispc, hw_plane, idx, in VID_REG_FLD_MOD()
462 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), in VID_REG_FLD_MOD()
526 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane) in dispc_vid_irq_from_raw() argument
536 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane) dispc_vid_irq_to_raw() argument
562 dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) dispc_k2g_vid_read_irqstatus() argument
570 dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k2g_vid_write_irqstatus() argument
594 dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) dispc_k2g_vid_read_irqenable() argument
602 dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k2g_vid_set_irqenable() argument
677 dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) dispc_k3_vid_read_irqstatus() argument
685 dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k3_vid_write_irqstatus() argument
709 dispc_k3_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) dispc_k3_vid_read_irqenable() argument
717 dispc_k3_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) dispc_k3_vid_set_irqenable() argument
1292 dispc_k2g_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_k2g_ovr_set_plane() argument
1301 dispc_am65x_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_am65x_ovr_set_plane() argument
1313 dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_j721e_ovr_set_plane() argument
1325 dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) dispc_ovr_set_plane() argument
1437 dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, const struct dispc_csc_coef *csc) dispc_k2g_vid_write_csc() argument
1460 dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, const struct dispc_csc_coef *csc) dispc_k3_vid_write_csc() argument
1557 dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state) dispc_vid_csc_setup() argument
1575 dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) dispc_vid_csc_enable() argument
1595 dispc_vid_write_fir_coefs(struct dispc_device *dispc, u32 hw_plane, enum dispc_vid_fir_coef_set coef_set, const struct tidss_scale_coefs *coefs) dispc_vid_write_fir_coefs() argument
1828 dispc_vid_set_scaling(struct dispc_device *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) dispc_vid_set_scaling() argument
1928 dispc_plane_set_pixel_format(struct dispc_device *dispc, u32 hw_plane, u32 fourcc) dispc_plane_set_pixel_format() argument
1967 dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) dispc_plane_check() argument
2038 dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) dispc_plane_setup() argument
2121 dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) dispc_plane_enable() argument
2126 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) dispc_vid_get_fifo_size() argument
2131 dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) dispc_vid_set_mflag_threshold() argument
2138 dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) dispc_vid_set_buf_threshold() argument
2147 unsigned int hw_plane; dispc_k2g_plane_init() local
2197 unsigned int hw_plane; dispc_k3_plane_init() local
[all...] |
| H A D | tidss_dispc.h | 97 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
125 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
128 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
131 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
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| H A D | tidss_plane.c | 32 u32 hw_plane = tplane->hw_plane_id; in tidss_plane_atomic_check() local
100 ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state, in tidss_plane_atomic_check()
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