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Searched refs:hw_ctl (Results 1 - 9 of 9) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_wb.c190 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_wb_setup_cdp()
193 (phys_enc->hw_ctl && in dpu_encoder_phys_wb_setup_cdp()
194 phys_enc->hw_ctl->ops.setup_intf_cfg)) { in dpu_encoder_phys_wb_setup_cdp()
216 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_cdp()
217 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_wb_setup_cdp()
224 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_cdp()
288 struct dpu_hw_ctl *hw_ctl; in _dpu_encoder_phys_wb_update_flush() local
527 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; dpu_encoder_phys_wb_disable() local
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H A Ddpu_encoder_phys_vid.c243 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_vid_setup_timing_engine()
287 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
306 struct dpu_hw_ctl *hw_ctl; in dpu_encoder_phys_vid_vblank_irq() local
310 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_vblank_irq()
324 if (hw_ctl->ops.get_flush_register) in dpu_encoder_phys_vid_vblank_irq()
325 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); in dpu_encoder_phys_vid_vblank_irq()
327 if (!(flush_register & hw_ctl in dpu_encoder_phys_vid_vblank_irq()
480 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; dpu_encoder_phys_vid_wait_for_commit_done() local
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H A Ddpu_encoder.c1054 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set() local
1086 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); in dpu_encoder_virt_atomic_mode_set()
1113 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); in dpu_encoder_virt_atomic_mode_set()
1130 if (!hw_ctl[i]) { in dpu_encoder_virt_atomic_mode_set()
1137 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); in dpu_encoder_virt_atomic_mode_set()
1493 ctl = phys->hw_ctl; in _dpu_encoder_trigger_flush()
1541 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1581 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
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H A Ddpu_encoder_phys_cmd.c55 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
154 phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; in dpu_encoder_phys_cmd_atomic_mode_set()
199 phys_enc->hw_ctl->idx - CTL_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
415 if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { in _dpu_encoder_phys_cmd_pingpong_config()
455 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_enable_helper()
563 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_disable()
687 if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) in dpu_encoder_phys_cmd_wait_for_commit_done()
H A Ddpu_encoder_phys.h152 * @hw_ctl: Hardware interface to the ctl registers
180 struct dpu_hw_ctl *hw_ctl; member
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_vid.c249 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_vid_setup_timing_engine()
289 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
306 struct dpu_hw_ctl *hw_ctl; in dpu_encoder_phys_vid_vblank_irq() local
310 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_vblank_irq()
326 if (hw_ctl->ops.get_flush_register) in dpu_encoder_phys_vid_vblank_irq()
327 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); in dpu_encoder_phys_vid_vblank_irq()
329 if (!(flush_register & hw_ctl in dpu_encoder_phys_vid_vblank_irq()
517 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; dpu_encoder_phys_vid_wait_for_commit_done() local
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H A Ddpu_encoder_phys_cmd.c60 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
148 irq->hw_idx = phys_enc->hw_ctl->idx; in _dpu_encoder_phys_cmd_setup_irq_hw_idx()
213 phys_enc->hw_ctl->idx - CTL_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
413 if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { in _dpu_encoder_phys_cmd_pingpong_config()
454 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_enable_helper()
H A Ddpu_encoder.c981 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_mode_set() local
1033 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); in dpu_encoder_virt_mode_set()
1050 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); in dpu_encoder_virt_mode_set()
1067 if (!hw_ctl[i]) { in dpu_encoder_virt_mode_set()
1074 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); in dpu_encoder_virt_mode_set()
1466 ctl = phys->hw_ctl; in _dpu_encoder_trigger_flush()
1511 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1550 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
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H A Ddpu_encoder_phys.h192 * @hw_ctl: Hardware interface to the ctl registers
221 struct dpu_hw_ctl *hw_ctl; member

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