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Searched refs:fp_vert_regs (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c314 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
315 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; in nv04_dfp_mode_set()
316 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; in nv04_dfp_mode_set()
317 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; in nv04_dfp_mode_set()
318 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; in nv04_dfp_mode_set()
319 regp->fp_vert_regs[FP_VALID_START] = 0; in nv04_dfp_mode_set()
320 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
412 regp->fp_vert_regs[FP_VALID_START] += diff / 2; in nv04_dfp_mode_set()
413 regp->fp_vert_regs[FP_VALID_END] -= diff / 2; in nv04_dfp_mode_set()
H A Dtvnv17.c541 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv17_tv_mode_set()
542 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; in nv17_tv_mode_set()
543 regs->fp_vert_regs[FP_SYNC_START] = in nv17_tv_mode_set()
545 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; in nv17_tv_mode_set()
546 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; in nv17_tv_mode_set()
H A Dtvmodesnv17.c574 regs->fp_vert_regs[FP_VALID_START] = vmargin; in nv17_ctv_update_rescaler()
575 regs->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - vmargin - 1; in nv17_ctv_update_rescaler()
587 regs->fp_vert_regs[FP_VALID_START]); in nv17_ctv_update_rescaler()
589 regs->fp_vert_regs[FP_VALID_END]); in nv17_ctv_update_rescaler()
H A Ddisp.h55 uint32_t fp_vert_regs[7]; member
H A Dhw.c427 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
505 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c314 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
315 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; in nv04_dfp_mode_set()
316 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; in nv04_dfp_mode_set()
317 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; in nv04_dfp_mode_set()
318 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; in nv04_dfp_mode_set()
319 regp->fp_vert_regs[FP_VALID_START] = 0; in nv04_dfp_mode_set()
320 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
412 regp->fp_vert_regs[FP_VALID_START] += diff / 2; in nv04_dfp_mode_set()
413 regp->fp_vert_regs[FP_VALID_END] -= diff / 2; in nv04_dfp_mode_set()
H A Dtvnv17.c542 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv17_tv_mode_set()
543 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; in nv17_tv_mode_set()
544 regs->fp_vert_regs[FP_SYNC_START] = in nv17_tv_mode_set()
546 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; in nv17_tv_mode_set()
547 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; in nv17_tv_mode_set()
H A Dtvmodesnv17.c573 regs->fp_vert_regs[FP_VALID_START] = vmargin; in nv17_ctv_update_rescaler()
574 regs->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - vmargin - 1; in nv17_ctv_update_rescaler()
586 regs->fp_vert_regs[FP_VALID_START]); in nv17_ctv_update_rescaler()
588 regs->fp_vert_regs[FP_VALID_END]); in nv17_ctv_update_rescaler()
H A Ddisp.h57 uint32_t fp_vert_regs[7]; member
H A Dhw.c429 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
507 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()

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