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Searched refs:emc_cfg (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/memory/tegra/
H A Dtegra30-emc.c340 u32 emc_cfg; member
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
536 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
537 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
650 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
678 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
681 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
683 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
685 writel_relaxed(emc->emc_cfg, em in emc_prepare_timing_change()
1010 u32 fbio_cfg5, emc_cfg, emc_dbg; emc_setup_hw() local
[all...]
H A Dtegra20-emc.c411 u32 emc_cfg, emc_dbg; in emc_setup_hw() local
413 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
419 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && in emc_setup_hw()
420 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { in emc_setup_hw()
427 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; in emc_setup_hw()
428 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
H A Dtegra124-emc.c449 u32 emc_cfg; member
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
813 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
859 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
922 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
H A Dtegra210-emc-cc-r21021.c480 u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value; in tegra210_emc_r21021_periodic_compensation() local
502 emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
611 u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock() local
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
666 emc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD | in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
752 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
/kernel/linux/linux-6.6/drivers/memory/tegra/
H A Dtegra30-emc.c370 u32 emc_cfg; member
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
577 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
578 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
691 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
719 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
722 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
724 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
726 writel_relaxed(emc->emc_cfg, em in emc_prepare_timing_change()
1120 u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg; emc_setup_hw() local
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H A Dtegra20-emc.c598 u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; in emc_setup_hw() local
605 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
611 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && in emc_setup_hw()
612 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { in emc_setup_hw()
619 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; in emc_setup_hw()
620 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
H A Dtegra124-emc.c456 u32 emc_cfg; member
705 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
842 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
960 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
H A Dtegra210-emc-cc-r21021.c480 u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value; in tegra210_emc_r21021_periodic_compensation() local
502 emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
611 u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock() local
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
666 emc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD | in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
752 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()

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