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Searched refs:ecc_ctrl (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v6_7.c495 uint32_t ecc_ctrl_addr, ecc_ctrl; in umc_v6_7_query_ras_poison_mode_per_channel() local
499 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
502 return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn); in umc_v6_7_query_ras_poison_mode_per_channel()
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
H A Drenesas-nand-controller.c205 u32 ecc_ctrl; member
312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG); in rnandc_select_target()
1036 rnand->ecc_ctrl |= ECC_CTRL_CAP_2B; in rnandc_hw_ecc_controller_init()
1040 rnand->ecc_ctrl |= ECC_CTRL_CAP_4B; in rnandc_hw_ecc_controller_init()
1044 rnand->ecc_ctrl |= ECC_CTRL_CAP_8B; in rnandc_hw_ecc_controller_init()
1048 rnand->ecc_ctrl |= ECC_CTRL_CAP_16B; in rnandc_hw_ecc_controller_init()
1052 rnand->ecc_ctrl |= ECC_CTRL_CAP_24B; in rnandc_hw_ecc_controller_init()
1056 rnand->ecc_ctrl |= ECC_CTRL_CAP_32B; in rnandc_hw_ecc_controller_init()
1063 rnand->ecc_ctrl |= ECC_CTRL_ERR_THRESHOLD(chip->ecc.strength); in rnandc_hw_ecc_controller_init()
/kernel/linux/linux-5.10/drivers/edac/
H A Damd64_edac.h339 u32 ecc_ctrl; /* DRAM ECC Control reg */ member
H A Dpnd2_edac.c437 static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS]; variable
493 if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) || in dnv_get_registers()
1101 if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) { in check_unit()
H A Damd64_edac.c859 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in __dump_misc_regs_df()
2767 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
2770 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
2808 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in __read_mc_regs_df()
/kernel/linux/linux-6.6/drivers/edac/
H A Damd64_edac.h311 u32 ecc_ctrl; /* DRAM ECC Control reg */ member
H A Dpnd2_edac.c415 static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS]; variable
471 if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) || in dnv_get_registers()
1079 if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) { in check_unit()
H A Damd64_edac.c1617 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in umc_dump_misc_regs()
3182 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in umc_read_mc_regs()
3815 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in gpu_dump_misc_regs()
3918 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in gpu_read_mc_regs()

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