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Searched refs:dsi_phy_write (Results 1 - 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm_8960.c16 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
20 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(bas in dsi_28nm_dphy_set_timing()
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H A Ddsi_phy_28nm.c14 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(bas in dsi_28nm_dphy_set_timing()
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H A Ddsi_phy_20nm.c14 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
33 dsi_phy_write(bas in dsi_20nm_dphy_set_timing()
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H A Ddsi_phy_7nm.c32 dsi_phy_write(lane_base + in dsi_phy_hw_v4_0_config_lpcdrx()
35 dsi_phy_write(lane_base + in dsi_phy_hw_v4_0_config_lpcdrx()
57 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0); in dsi_phy_hw_v4_0_lane_settings()
58 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0); in dsi_phy_hw_v4_0_lane_settings()
65 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0); in dsi_phy_hw_v4_0_lane_settings()
66 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0); in dsi_phy_hw_v4_0_lane_settings()
67 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa); in dsi_phy_hw_v4_0_lane_settings()
68 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]); in dsi_phy_hw_v4_0_lane_settings()
127 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); in dsi_7nm_phy_enable()
130 dsi_phy_write(bas in dsi_7nm_phy_enable()
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H A Ddsi_phy_10nm.c32 dsi_phy_write(lane_base + in dsi_phy_hw_v3_0_config_lpcdrx()
35 dsi_phy_write(lane_base + in dsi_phy_hw_v3_0_config_lpcdrx()
50 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i), in dsi_phy_hw_v3_0_lane_settings()
57 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0); in dsi_phy_hw_v3_0_lane_settings()
58 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
59 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i), in dsi_phy_hw_v3_0_lane_settings()
67 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
68 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
69 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
70 dsi_phy_write(lane_bas in dsi_phy_hw_v3_0_lane_settings()
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H A Ddsi_phy_14nm.c27 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), in dsi_14nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), in dsi_14nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), in dsi_14nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), in dsi_14nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), in dsi_14nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), in dsi_14nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), in dsi_14nm_dphy_set_timing()
41 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), in dsi_14nm_dphy_set_timing()
44 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), in dsi_14nm_dphy_set_timing()
46 dsi_phy_write(bas in dsi_14nm_dphy_set_timing()
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H A Ddsi_phy.h14 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) macro
H A Ddsi_phy.c475 dsi_phy_write(phy->base + reg, val | bit_mask); in msm_dsi_phy_set_src_pll()
477 dsi_phy_write(phy->base + reg, val & (~bit_mask)); in msm_dsi_phy_set_src_pll()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c15 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
17 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
19 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
30 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
32 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
34 dsi_phy_write(bas in dsi_20nm_dphy_set_timing()
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H A Ddsi_phy_10nm.c190 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, in dsi_pll_ssc_commit()
192 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, in dsi_pll_ssc_commit()
194 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, in dsi_pll_ssc_commit()
196 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, in dsi_pll_ssc_commit()
198 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, in dsi_pll_ssc_commit()
200 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, in dsi_pll_ssc_commit()
202 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
211 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); in dsi_pll_config_hzindep_reg()
212 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); in dsi_pll_config_hzindep_reg()
213 dsi_phy_write(bas in dsi_pll_config_hzindep_reg()
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H A Ddsi_phy_28nm_8960.c106 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, in dsi_pll_28nm_clk_set_rate()
113 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, in dsi_pll_28nm_clk_set_rate()
120 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, in dsi_pll_28nm_clk_set_rate()
123 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, in dsi_pll_28nm_clk_set_rate()
128 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, in dsi_pll_28nm_clk_set_rate()
205 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); in dsi_pll_28nm_vco_prepare()
208 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, in dsi_pll_28nm_vco_prepare()
233 dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); in dsi_pll_28nm_vco_unprepare()
328 dsi_phy_write(bytediv->reg, val); in clk_bytediv_set_rate()
374 dsi_phy_write(bas in dsi_28nm_pll_restore_state()
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H A Ddsi_phy_7nm.c197 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, in dsi_pll_ssc_commit()
199 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, in dsi_pll_ssc_commit()
201 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, in dsi_pll_ssc_commit()
203 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, in dsi_pll_ssc_commit()
205 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, in dsi_pll_ssc_commit()
207 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, in dsi_pll_ssc_commit()
209 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
245 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, in dsi_pll_config_hzindep_reg()
247 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); in dsi_pll_config_hzindep_reg()
248 dsi_phy_write(bas in dsi_pll_config_hzindep_reg()
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H A Ddsi_phy_28nm.c131 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); in dsi_pll_28nm_clk_set_rate()
142 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); in dsi_pll_28nm_clk_set_rate()
145 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate()
146 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate()
198 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); in dsi_pll_28nm_clk_set_rate()
199 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); in dsi_pll_28nm_clk_set_rate()
200 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); in dsi_pll_28nm_clk_set_rate()
201 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); in dsi_pll_28nm_clk_set_rate()
203 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
204 dsi_phy_write(bas in dsi_pll_28nm_clk_set_rate()
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H A Ddsi_phy_14nm.c291 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); in pll_db_commit_ssc()
294 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); in pll_db_commit_ssc()
298 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); in pll_db_commit_ssc()
301 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); in pll_db_commit_ssc()
305 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); in pll_db_commit_ssc()
308 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); in pll_db_commit_ssc()
313 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); in pll_db_commit_ssc()
326 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); in pll_db_commit_common()
328 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1); in pll_db_commit_common()
330 dsi_phy_write(bas in pll_db_commit_common()
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H A Ddsi_phy.h16 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) macro

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