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Help
Searched
refs:dsi_phy_read
(Results
1 - 12
of
12
) sorted by relevance
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H
A
D
dsi_phy_28nm_8960.c
77
val =
dsi_phy_read
(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY);
in pll_28nm_poll_for_ready()
109
val =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
in dsi_pll_28nm_clk_set_rate()
116
val =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
in dsi_pll_28nm_clk_set_rate()
126
val =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
in dsi_pll_28nm_clk_set_rate()
152
status =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
in dsi_pll_28nm_clk_recalc_rate()
155
fb_divider =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
in dsi_pll_28nm_clk_recalc_rate()
157
temp =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
in dsi_pll_28nm_clk_recalc_rate()
161
ref_divider =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
in dsi_pll_28nm_clk_recalc_rate()
198
val =
dsi_phy_read
(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
in dsi_pll_28nm_vco_prepare()
202
val =
dsi_phy_read
(bas
in dsi_pll_28nm_vco_prepare()
[all...]
H
A
D
dsi_phy_10nm.c
308
u32 data =
dsi_phy_read
(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
in dsi_pll_disable_pll_bias()
318
u32 data =
dsi_phy_read
(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
in dsi_pll_enable_pll_bias()
330
data =
dsi_phy_read
(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
in dsi_pll_disable_global_clk()
339
data =
dsi_phy_read
(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
in dsi_pll_enable_global_clk()
432
dec =
dsi_phy_read
(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
in dsi_pll_10nm_vco_recalc_rate()
435
frac =
dsi_phy_read
(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
in dsi_pll_10nm_vco_recalc_rate()
436
frac |= ((
dsi_phy_read
(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
in dsi_pll_10nm_vco_recalc_rate()
438
frac |= ((
dsi_phy_read
(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
in dsi_pll_10nm_vco_recalc_rate()
491
cached->pll_out_div =
dsi_phy_read
(pll_10nm->phy->pll_base +
in dsi_10nm_pll_save_state()
495
cmn_clk_cfg0 =
dsi_phy_read
(phy_bas
in dsi_10nm_pll_save_state()
[all...]
H
A
D
dsi_phy_7nm.c
350
u32 data =
dsi_phy_read
(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
in dsi_pll_disable_pll_bias()
359
u32 data =
dsi_phy_read
(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
in dsi_pll_enable_pll_bias()
370
data =
dsi_phy_read
(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
in dsi_pll_disable_global_clk()
380
data =
dsi_phy_read
(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
in dsi_pll_enable_global_clk()
481
dec =
dsi_phy_read
(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
in dsi_pll_7nm_vco_recalc_rate()
484
frac =
dsi_phy_read
(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
in dsi_pll_7nm_vco_recalc_rate()
485
frac |= ((
dsi_phy_read
(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
in dsi_pll_7nm_vco_recalc_rate()
487
frac |= ((
dsi_phy_read
(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
in dsi_pll_7nm_vco_recalc_rate()
540
cached->pll_out_div =
dsi_phy_read
(pll_7nm->phy->pll_base +
in dsi_7nm_pll_save_state()
544
cmn_clk_cfg0 =
dsi_phy_read
(phy_bas
in dsi_7nm_pll_save_state()
[all...]
H
A
D
dsi_phy_28nm.c
86
val =
dsi_phy_read
(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);
in pll_28nm_poll_for_ready()
171
sdm_cfg1 =
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
in dsi_pll_28nm_clk_set_rate()
253
doubler =
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
in dsi_pll_28nm_clk_recalc_rate()
258
sdm0 =
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
in dsi_pll_28nm_clk_recalc_rate()
262
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
in dsi_pll_28nm_clk_recalc_rate()
268
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
in dsi_pll_28nm_clk_recalc_rate()
271
sdm2 = FIELD(
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
in dsi_pll_28nm_clk_recalc_rate()
273
sdm3 = FIELD(
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
in dsi_pll_28nm_clk_recalc_rate()
563
dsi_phy_read
(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
in dsi_28nm_pll_save_state()
565
dsi_phy_read
(bas
in dsi_28nm_pll_save_state()
[all...]
H
A
D
dsi_phy_14nm.c
119
val =
dsi_phy_read
(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
in pll_14nm_poll_for_ready()
133
val =
dsi_phy_read
(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
in pll_14nm_poll_for_ready()
500
dec_start =
dsi_phy_read
(base + REG_DSI_14nm_PHY_PLL_DEC_START);
in dsi_pll_14nm_vco_recalc_rate()
505
div_frac_start = (
dsi_phy_read
(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
in dsi_pll_14nm_vco_recalc_rate()
507
div_frac_start |= (
dsi_phy_read
(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
in dsi_pll_14nm_vco_recalc_rate()
509
div_frac_start |=
dsi_phy_read
(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
in dsi_pll_14nm_vco_recalc_rate()
614
val =
dsi_phy_read
(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
in dsi_pll_14nm_postdiv_recalc_rate()
656
val =
dsi_phy_read
(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
in dsi_pll_14nm_postdiv_set_rate()
694
data =
dsi_phy_read
(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
in dsi_14nm_pll_save_state()
1001
glbl_test_ctrl =
dsi_phy_read
(bas
in dsi_14nm_phy_enable()
[all...]
H
A
D
dsi_phy.h
15
#define
dsi_phy_read
(offset) msm_readl((offset))
macro
H
A
D
dsi_phy_20nm.c
88
val =
dsi_phy_read
(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
in dsi_20nm_phy_enable()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
H
A
D
dsi_phy_7nm.c
16
data =
dsi_phy_read
(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
in dsi_phy_hw_v4_0_is_pll_on()
136
data =
dsi_phy_read
(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
in dsi_7nm_phy_enable()
H
A
D
dsi_phy_10nm.c
16
data =
dsi_phy_read
(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
in dsi_phy_hw_v3_0_is_pll_on()
168
data =
dsi_phy_read
(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
in dsi_10nm_phy_enable()
H
A
D
dsi_phy.h
13
#define
dsi_phy_read
(offset) msm_readl((offset))
macro
H
A
D
dsi_phy_28nm_8960.c
85
status =
dsi_phy_read
(base +
in dsi_28nm_phy_calibration()
H
A
D
dsi_phy.c
472
val =
dsi_phy_read
(phy->base + reg);
in msm_dsi_phy_set_src_pll()
Completed in 9 milliseconds