| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 601 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table()
611 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
618 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
619 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
638 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
641 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
644 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
646 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCL in vega12_setup_default_dpm_tables()
600 vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) vega12_setup_single_dpm_table() argument
1851 struct vega12_single_dpm_table *dpm_table; vega12_get_sclks() local
1884 struct vega12_single_dpm_table *dpm_table; vega12_get_memclocks() local
1911 struct vega12_single_dpm_table *dpm_table; vega12_get_dcefclocks() local
1939 struct vega12_single_dpm_table *dpm_table; vega12_get_socclocks() local
2351 struct vega12_single_dpm_table *dpm_table; vega12_apply_clocks_adjust_rules() local
2508 vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table) vega12_set_uclk_to_highest_dpm_level() argument
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| H A D | vega20_hwmgr.c | 558 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table()
568 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
575 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
576 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
586 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
589 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
591 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
596 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
597 dpm_table in vega20_setup_gfxclk_dpm_table()
557 vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) vega20_setup_single_dpm_table() argument
607 struct vega20_single_dpm_table *dpm_table; vega20_setup_memclk_dpm_table() local
636 struct vega20_single_dpm_table *dpm_table; vega20_setup_default_dpm_tables() local
2341 struct vega20_single_dpm_table *dpm_table = vega20_notify_smc_display_config_after_ps_adjustment() local
2808 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); vega20_get_sclks() local
2836 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); vega20_get_memclocks() local
2861 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); vega20_get_dcefclocks() local
2883 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); vega20_get_socclocks() local
3573 vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table) vega20_set_uclk_to_highest_dpm_level() argument
3602 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); vega20_set_fclk_to_highest_dpm_level() local
3731 struct vega20_single_dpm_table *dpm_table; vega20_apply_clocks_adjust_rules() local
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| H A D | vega10_hwmgr.c | 1230 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table()
1235 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1238 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1240 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1242 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1243 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1250 struct vega10_pcie_table *pcie_table = &(data->dpm_table in vega10_setup_default_pcie_table()
1229 vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) vega10_setup_default_single_dpm_table() argument
1301 struct vega10_single_dpm_table *dpm_table; vega10_setup_default_dpm_tables() local
1722 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); vega10_populate_all_graphic_levels() local
1871 struct vega10_single_dpm_table *dpm_table = vega10_populate_all_memory_levels() local
2009 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); vega10_populate_smc_vce_levels() local
3460 struct vega10_dpm_table *dpm_table = &data->dpm_table; vega10_populate_and_upload_sclk_mclk_dpm_levels() local
3500 vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) vega10_trim_single_dpm_states() argument
3516 vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit, uint32_t disable_dpm_mask) vega10_trim_single_dpm_states_with_mask() argument
3921 struct vega10_dpm_table *dpm_table = &data->dpm_table; vega10_read_sensor() local
4063 struct vega10_single_dpm_table *dpm_table = vega10_notify_smc_display_config_after_ps_adjustment() local
5469 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; vega10_odn_update_soc_table() local
5540 struct vega10_single_dpm_table *dpm_table; vega10_odn_edit_dpm_table() local
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| H A D | smu_helper.c | 351 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
353 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
355 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
356 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
366 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
367 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
369 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
376 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
378 for (i = dpm_table in phm_get_dpm_level_enable_mask_value()
448 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; phm_find_boot_level() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 602 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table()
612 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
619 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
620 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
639 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
642 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
645 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
647 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCL in vega12_setup_default_dpm_tables()
601 vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) vega12_setup_single_dpm_table() argument
1831 struct vega12_single_dpm_table *dpm_table; vega12_get_sclks() local
1864 struct vega12_single_dpm_table *dpm_table; vega12_get_memclocks() local
1891 struct vega12_single_dpm_table *dpm_table; vega12_get_dcefclocks() local
1919 struct vega12_single_dpm_table *dpm_table; vega12_get_socclocks() local
2329 struct vega12_single_dpm_table *dpm_table; vega12_apply_clocks_adjust_rules() local
2486 vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table) vega12_set_uclk_to_highest_dpm_level() argument
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| H A D | vega20_hwmgr.c | 559 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table()
569 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
576 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
577 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
587 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
590 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
592 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
597 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
598 dpm_table in vega20_setup_gfxclk_dpm_table()
558 vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) vega20_setup_single_dpm_table() argument
608 struct vega20_single_dpm_table *dpm_table; vega20_setup_memclk_dpm_table() local
637 struct vega20_single_dpm_table *dpm_table; vega20_setup_default_dpm_tables() local
2341 struct vega20_single_dpm_table *dpm_table = vega20_notify_smc_display_config_after_ps_adjustment() local
2808 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); vega20_get_sclks() local
2836 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); vega20_get_memclocks() local
2861 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); vega20_get_dcefclocks() local
2883 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); vega20_get_socclocks() local
3571 vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table) vega20_set_uclk_to_highest_dpm_level() argument
3600 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); vega20_set_fclk_to_highest_dpm_level() local
3729 struct vega20_single_dpm_table *dpm_table; vega20_apply_clocks_adjust_rules() local
[all...] |
| H A D | vega10_hwmgr.c | 1232 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table()
1237 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1240 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1242 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1244 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1245 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1252 struct vega10_pcie_table *pcie_table = &(data->dpm_table in vega10_setup_default_pcie_table()
1231 vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) vega10_setup_default_single_dpm_table() argument
1303 struct vega10_single_dpm_table *dpm_table; vega10_setup_default_dpm_tables() local
1723 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); vega10_populate_all_graphic_levels() local
1871 struct vega10_single_dpm_table *dpm_table = vega10_populate_all_memory_levels() local
2009 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); vega10_populate_smc_vce_levels() local
3433 struct vega10_dpm_table *dpm_table = &data->dpm_table; vega10_populate_and_upload_sclk_mclk_dpm_levels() local
3473 vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) vega10_trim_single_dpm_states() argument
3489 vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit, uint32_t disable_dpm_mask) vega10_trim_single_dpm_states_with_mask() argument
3894 struct vega10_dpm_table *dpm_table = &data->dpm_table; vega10_read_sensor() local
4036 struct vega10_single_dpm_table *dpm_table = vega10_notify_smc_display_config_after_ps_adjustment() local
5285 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; vega10_odn_update_soc_table() local
5356 struct vega10_single_dpm_table *dpm_table; vega10_odn_edit_dpm_table() local
[all...] |
| H A D | smu7_hwmgr.c | 600 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
611 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
617 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
621 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
626 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
631 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
636 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
641 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
646 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
652 data->dpm_table in smu7_setup_default_pcie_table()
3748 struct smu7_dpm_table *dpm_table = &data->dpm_table; smu7_get_maximum_link_speed() local
3857 struct smu7_dpm_table *dpm_table = &data->dpm_table; smu7_populate_and_upload_sclk_mclk_dpm_levels() local
3900 smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct smu7_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) smu7_trim_single_dpm_states() argument
[all...] |
| H A D | smu_helper.c | 351 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
353 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
355 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
356 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
366 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
367 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
369 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
376 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
378 for (i = dpm_table in phm_get_dpm_level_enable_mask_value()
448 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; phm_find_boot_level() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | navi10_ppt.c | 651 struct smu_11_0_dpm_table *dpm_table; in navi10_set_default_dpm_table() local
655 dpm_table = &dpm_context->dpm_tables.soc_table; in navi10_set_default_dpm_table()
659 dpm_table); in navi10_set_default_dpm_table()
662 dpm_table->is_fine_grained = in navi10_set_default_dpm_table()
665 dpm_table->count = 1; in navi10_set_default_dpm_table()
666 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
667 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
668 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
669 dpm_table in navi10_set_default_dpm_table()
[all...] |
| H A D | sienna_cichlid_ppt.c | 583 struct smu_11_0_dpm_table *dpm_table; in sienna_cichlid_set_default_dpm_table() local
588 dpm_table = &dpm_context->dpm_tables.soc_table; in sienna_cichlid_set_default_dpm_table()
592 dpm_table); in sienna_cichlid_set_default_dpm_table()
595 dpm_table->is_fine_grained = in sienna_cichlid_set_default_dpm_table()
598 dpm_table->count = 1; in sienna_cichlid_set_default_dpm_table()
599 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
600 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
601 dpm_table->min = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
602 dpm_table in sienna_cichlid_set_default_dpm_table()
[all...] |
| H A D | arcturus_ppt.c | 304 struct smu_11_0_dpm_table *dpm_table = NULL; in arcturus_set_default_dpm_table() local
308 dpm_table = &dpm_context->dpm_tables.soc_table; in arcturus_set_default_dpm_table()
312 dpm_table); in arcturus_set_default_dpm_table()
315 dpm_table->is_fine_grained = in arcturus_set_default_dpm_table()
318 dpm_table->count = 1; in arcturus_set_default_dpm_table()
319 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
320 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
321 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
322 dpm_table in arcturus_set_default_dpm_table()
533 arcturus_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_11_0_dpm_table *dpm_table) arcturus_get_clk_table() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_7_ppt.c | 573 struct smu_13_0_dpm_table *dpm_table; in smu_v13_0_7_set_default_dpm_table() local
579 dpm_table = &dpm_context->dpm_tables.soc_table; in smu_v13_0_7_set_default_dpm_table()
583 dpm_table); in smu_v13_0_7_set_default_dpm_table()
587 dpm_table->count = 1; in smu_v13_0_7_set_default_dpm_table()
588 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_7_set_default_dpm_table()
589 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
590 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_7_set_default_dpm_table()
591 dpm_table->max = dpm_table in smu_v13_0_7_set_default_dpm_table()
870 struct smu_13_0_dpm_table *dpm_table; smu_v13_0_7_get_dpm_ultimate_freq() local
[all...] |
| H A D | smu_v13_0_0_ppt.c | 574 struct smu_13_0_dpm_table *dpm_table; in smu_v13_0_0_set_default_dpm_table() local
580 dpm_table = &dpm_context->dpm_tables.soc_table; in smu_v13_0_0_set_default_dpm_table()
584 dpm_table); in smu_v13_0_0_set_default_dpm_table()
588 dpm_table->count = 1; in smu_v13_0_0_set_default_dpm_table()
589 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_0_set_default_dpm_table()
590 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
591 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_0_set_default_dpm_table()
592 dpm_table->max = dpm_table in smu_v13_0_0_set_default_dpm_table()
889 struct smu_13_0_dpm_table *dpm_table; smu_v13_0_0_get_dpm_ultimate_freq() local
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| H A D | aldebaran_ppt.c | 312 struct smu_13_0_dpm_table *dpm_table = NULL; in aldebaran_set_default_dpm_table() local
317 dpm_table = &dpm_context->dpm_tables.soc_table; in aldebaran_set_default_dpm_table()
321 dpm_table); in aldebaran_set_default_dpm_table()
325 dpm_table->count = 1; in aldebaran_set_default_dpm_table()
326 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in aldebaran_set_default_dpm_table()
327 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
328 dpm_table->min = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
329 dpm_table->max = dpm_table in aldebaran_set_default_dpm_table()
556 aldebaran_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_13_0_dpm_table *dpm_table) aldebaran_get_clk_table() argument
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| H A D | smu_v13_0_6_ppt.c | 214 struct smu_13_0_dpm_table *dpm_table; member
487 struct smu_13_0_dpm_table *dpm_table = NULL; in smu_v13_0_6_set_default_dpm_table() local
513 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_6_set_default_dpm_table()
523 dpm_table->count = 2; in smu_v13_0_6_set_default_dpm_table()
524 dpm_table->dpm_levels[0].value = gfxclkmin; in smu_v13_0_6_set_default_dpm_table()
525 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_6_set_default_dpm_table()
526 dpm_table->dpm_levels[1].value = gfxclkmax; in smu_v13_0_6_set_default_dpm_table()
527 dpm_table->dpm_levels[1].enabled = true; in smu_v13_0_6_set_default_dpm_table()
528 dpm_table->min = dpm_table in smu_v13_0_6_set_default_dpm_table()
637 smu_v13_0_6_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_13_0_dpm_table *dpm_table) smu_v13_0_6_get_clk_table() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | navi10_ppt.c | 973 struct smu_11_0_dpm_table *dpm_table; in navi10_set_default_dpm_table() local
977 dpm_table = &dpm_context->dpm_tables.soc_table; in navi10_set_default_dpm_table()
981 dpm_table); in navi10_set_default_dpm_table()
984 dpm_table->is_fine_grained = in navi10_set_default_dpm_table()
987 dpm_table->count = 1; in navi10_set_default_dpm_table()
988 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
989 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
990 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
991 dpm_table in navi10_set_default_dpm_table()
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| H A D | arcturus_ppt.c | 331 struct smu_11_0_dpm_table *dpm_table = NULL; in arcturus_set_default_dpm_table() local
335 dpm_table = &dpm_context->dpm_tables.soc_table; in arcturus_set_default_dpm_table()
339 dpm_table); in arcturus_set_default_dpm_table()
342 dpm_table->is_fine_grained = in arcturus_set_default_dpm_table()
345 dpm_table->count = 1; in arcturus_set_default_dpm_table()
346 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
347 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
348 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
349 dpm_table in arcturus_set_default_dpm_table()
572 arcturus_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_11_0_dpm_table *dpm_table) arcturus_get_clk_table() argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | fiji_smumgr.c | 491 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
503 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
505 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
512 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
513 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
515 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
518 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
520 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
522 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
524 dpm_table in fiji_populate_bapm_parameters_in_dpm_table()
831 struct smu7_dpm_table *dpm_table = &data->dpm_table; fiji_populate_smc_link_level() local
1005 struct smu7_dpm_table *dpm_table = &data->dpm_table; fiji_populate_all_graphic_levels() local
1224 struct smu7_dpm_table *dpm_table = &data->dpm_table; fiji_populate_all_memory_levels() local
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| H A D | iceland_smumgr.c | 767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
771 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ in iceland_populate_smc_link_level()
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
1350 struct smu7_dpm_table *dpm_table = &data->dpm_table; iceland_populate_all_memory_levels() local
1854 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); iceland_populate_bapm_parameters_in_dpm_table() local
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| H A D | ci_smumgr.c | 475 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
485 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
487 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
493 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
500 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
502 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
719 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
725 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
726 dpm_table in ci_populate_bapm_parameters_in_dpm_table()
999 struct smu7_dpm_table *dpm_table = &data->dpm_table; ci_populate_smc_link_level() local
1303 struct smu7_dpm_table *dpm_table = &data->dpm_table; ci_populate_all_memory_levels() local
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | fiji_smumgr.c | 490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
502 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
504 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
511 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
512 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
514 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
517 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
519 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
521 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
523 dpm_table in fiji_populate_bapm_parameters_in_dpm_table()
830 struct smu7_dpm_table *dpm_table = &data->dpm_table; fiji_populate_smc_link_level() local
1004 struct smu7_dpm_table *dpm_table = &data->dpm_table; fiji_populate_all_graphic_levels() local
1223 struct smu7_dpm_table *dpm_table = &data->dpm_table; fiji_populate_all_memory_levels() local
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| H A D | iceland_smumgr.c | 767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
771 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ in iceland_populate_smc_link_level()
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
1350 struct smu7_dpm_table *dpm_table = &data->dpm_table; iceland_populate_all_memory_levels() local
1854 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); iceland_populate_bapm_parameters_in_dpm_table() local
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | ci_dpm.c | 420 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
428 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
429 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
431 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
432 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
434 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
436 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
439 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
440 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
442 dpm_table in ci_populate_bapm_parameters_in_dpm_table()
2595 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) ci_get_dpm_level_enable_mask_value() argument
2615 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_smc_link_level() local
3264 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_all_graphic_levels() local
3311 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_all_memory_levels() local
3359 ci_reset_single_dpm_table(struct radeon_device *rdev, struct ci_single_dpm_table* dpm_table, u32 count) ci_reset_single_dpm_table() argument
3370 ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, u32 index, u32 pcie_gen, u32 pcie_lanes) ci_setup_pcie_table_entry() argument
3688 ci_trim_single_dpm_states(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 low_limit, u32 high_limit) ci_trim_single_dpm_states() argument
3889 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_and_upload_sclk_mclk_dpm_levels() local
5673 SMU7_Discrete_DpmTable *dpm_table; ci_dpm_init() local
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | ci_dpm.c | 410 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
418 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
422 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
424 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
426 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
429 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
430 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
432 dpm_table in ci_populate_bapm_parameters_in_dpm_table()
2571 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) ci_get_dpm_level_enable_mask_value() argument
2591 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_smc_link_level() local
3240 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_all_graphic_levels() local
3287 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_all_memory_levels() local
3335 ci_reset_single_dpm_table(struct radeon_device *rdev, struct ci_single_dpm_table* dpm_table, u32 count) ci_reset_single_dpm_table() argument
3346 ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, u32 index, u32 pcie_gen, u32 pcie_lanes) ci_setup_pcie_table_entry() argument
3664 ci_trim_single_dpm_states(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 low_limit, u32 high_limit) ci_trim_single_dpm_states() argument
3865 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_and_upload_sclk_mclk_dpm_levels() local
5649 SMU7_Discrete_DpmTable *dpm_table; ci_dpm_init() local
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