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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile71 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
72 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
73 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
74 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
75 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
76 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
77 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
78 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
79 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
80 CFLAGS_$(AMDDALPATH)/dc/dml/dcn2
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile58 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
63 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
64 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
65 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
66 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
67 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
68 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
69 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn2
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c294 if (dc->dml.ip.writeback_max_hscl_taps > 1) { in dcn30_fpu_populate_dml_writeback_from_context()
334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_fpu_populate_dml_writeback_from_context()
348 struct display_mode_lib *dml, in dcn30_fpu_set_mcif_arb_params()
358 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_fpu_set_mcif_arb_params()
359 wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in dcn30_fpu_set_mcif_arb_params()
362 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ in dcn30_fpu_set_mcif_arb_params()
372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_update_soc_for_wm_a()
374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; in dcn30_fpu_update_soc_for_wm_a()
375 context->bw_ctx.dml in dcn30_fpu_update_soc_for_wm_a()
347 dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt, int cur_pipe) dcn30_fpu_set_mcif_arb_params() argument
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H A Ddcn30_fpu.h39 struct display_mode_lib *dml,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c31 #include "dml/dcn20/dcn20_fpu.h"
295 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel()
299 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
307 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
308 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
309 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipe in calculate_wm_set_for_vlevel()
292 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) calculate_wm_set_for_vlevel() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c32 #include "dml/dcn20/dcn20_fpu.h"
457 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn31_update_soc_for_wm_a()
458 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn31_update_soc_for_wm_a()
459 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn31_update_soc_for_wm_a()
469 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_vactive) in dcn315_update_soc_for_wm_a()
470 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn315_update_soc_for_wm_a()
472 context->bw_ctx.dml in dcn315_update_soc_for_wm_a()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c30 #include "dml/dcn32/display_mode_vba_32.h"
176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
177 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
178 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
179 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
184 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
269 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
271 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
277 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
278 context->bw_ctx.dml in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1037 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn20_fpu_set_wb_arb_params()
1038 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn20_fpu_set_wb_arb_params()
1083 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1090 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1147 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1148 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1149 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1150 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml in dcn20_calculate_dlg_params()
2200 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) calculate_wm_set_for_vlevel() argument
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/kernel/linux/linux-5.10/net/packet/
H A Ddiag.c49 struct packet_diag_mclist *dml; in pdiag_put_mclist() local
51 dml = nla_reserve_nohdr(nlskb, sizeof(*dml)); in pdiag_put_mclist()
52 if (!dml) { in pdiag_put_mclist()
58 dml->pdmc_index = ml->ifindex; in pdiag_put_mclist()
59 dml->pdmc_type = ml->type; in pdiag_put_mclist()
60 dml->pdmc_alen = ml->alen; in pdiag_put_mclist()
61 dml->pdmc_count = ml->count; in pdiag_put_mclist()
62 BUILD_BUG_ON(sizeof(dml->pdmc_addr) != sizeof(ml->addr)); in pdiag_put_mclist()
63 memcpy(dml in pdiag_put_mclist()
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/kernel/linux/linux-6.6/net/packet/
H A Ddiag.c49 struct packet_diag_mclist *dml; in pdiag_put_mclist() local
51 dml = nla_reserve_nohdr(nlskb, sizeof(*dml)); in pdiag_put_mclist()
52 if (!dml) { in pdiag_put_mclist()
58 dml->pdmc_index = ml->ifindex; in pdiag_put_mclist()
59 dml->pdmc_type = ml->type; in pdiag_put_mclist()
60 dml->pdmc_alen = ml->alen; in pdiag_put_mclist()
61 dml->pdmc_count = ml->count; in pdiag_put_mclist()
62 BUILD_BUG_ON(sizeof(dml->pdmc_addr) != sizeof(ml->addr)); in pdiag_put_mclist()
63 memcpy(dml in pdiag_put_mclist()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c60 #include "dml/display_mode_vba.h"
86 #include "dml/dcn30/display_mode_vba_30.h"
1503 if (dc->dml.ip.writeback_max_hscl_taps > 1) { in dcn30_populate_dml_writeback_from_context()
1543 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_populate_dml_writeback_from_context()
1587 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1614 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_set_mcif_arb_params()
1615 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in dcn30_set_mcif_arb_params()
1623 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ in dcn30_set_mcif_arb_params()
1957 struct vba_vars_st *vba = &context->bw_ctx.dml in dcn30_internal_validate_bw()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c35 #include "dml/dml1_display_rq_dlg_calc.h"
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
497 // dc->dml.logger = pool->base.logger; in dcn_bw_calc_rq_dlg_ttu()
505 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); in dcn_bw_calc_rq_dlg_ttu()
506 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
508 dml, in dcn_bw_calc_rq_dlg_ttu()
1093 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
1094 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; in dcn_validate_bandwidth()
1309 context->bw_ctx.dml in dcn_validate_bandwidth()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c35 #include "dml/dml1_display_rq_dlg_calc.h"
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
500 // dc->dml.logger = pool->base.logger; in dcn_bw_calc_rq_dlg_ttu()
507 dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src); in dcn_bw_calc_rq_dlg_ttu()
508 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
510 dml, in dcn_bw_calc_rq_dlg_ttu()
1078 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
1079 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; in dcn_validate_bandwidth()
1294 context->bw_ctx.dml in dcn_validate_bandwidth()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c60 #include "dml/display_mode_vba.h"
2221 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2457 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2458 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2660 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2715 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2720 if (vlevel > context->bw_ctx.dml.soc.num_states)
2729 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2865 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2867 if (vlevel > context->bw_ctx.dml
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c59 #include "dml/display_mode_vba.h"
1029 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel()
1033 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
1035 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1039 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1041 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
1042 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
1043 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; in calculate_wm_set_for_vlevel()
1045 wm_set->urgent_ns = get_wm_urgent(dml, pipe in calculate_wm_set_for_vlevel()
1025 calculate_wm_set_for_vlevel( int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) calculate_wm_set_for_vlevel() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn10/
H A Ddcn10_fpu.c133 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp() local
135 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c31 #include "dml/dcn20/dcn20_fpu.h"
32 #include "dml/dcn31/dcn31_fpu.h"
33 #include "dml/display_mode_vba.h"
34 #include "dml/dml_inline_defs.h"
265 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn314_update_bw_bounding_box_fpu()
269 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314); in dcn314_update_bw_bounding_box_fpu()
392 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
402 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
407 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
409 context->bw_ctx.dml in dcn314_populate_dml_pipes_from_context_fpu()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c60 #include "dml/display_mode_vba.h"
87 #include "dml/dcn30/dcn30_fpu.h"
88 #include "dml/dcn30/display_mode_vba_30.h"
1378 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1405 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); in dcn30_set_mcif_arb_params()
1640 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1647 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1648 context->bw_ctx.dml in dcn30_internal_validate_bw()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c31 #include "dml/dcn20/dcn20_fpu.h"
218 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn302_fpu_update_bw_bounding_box()
333 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_fpu_update_bw_bounding_box()
335 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_fpu_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c30 #include "dml/dcn20/dcn20_fpu.h"
214 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn303_fpu_update_bw_bounding_box()
341 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_fpu_update_bw_bounding_box()
343 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_fpu_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c39 #include "dml/dcn20/dcn20_fpu.h"
61 #include "dml/display_mode_vba.h"
826 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
828 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
830 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
838 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
840 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
841 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
850 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
880 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml in dcn21_fast_validate_bw()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
H A DMakefile31 DC_LIBS += dcn10 dml
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn3_build_wm_range_table()
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table()
139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us; in dcn3_build_wm_range_table()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual dsc
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c38 #include "dml/dcn20/dcn20_fpu.h"
62 #include "dml/display_mode_vba.h"
1841 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1901 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1910 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ in dcn20_validate_apply_pipe_split_flags()
2048 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2050 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2068 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2087 && context->bw_ctx.dml in dcn20_fast_validate_bw()
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