Searched refs:divsel (Results 1 - 6 of 6) sorted by relevance
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_pch_refclk.c | 123 u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor; member
153 p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2; in lpt_compute_iclkip()
160 if (p->divsel <= 0x7f) in lpt_compute_iclkip()
189 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) & in lpt_program_iclkip()
195 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", in lpt_program_iclkip()
196 clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc); in lpt_program_iclkip()
203 temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel); in lpt_program_iclkip()
248 p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> in lpt_get_iclkip()
259 p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc; in lpt_get_iclkip()
|
| /kernel/linux/linux-5.10/drivers/mfd/ |
| H A D | db8500-prcmu.c | 505 u32 divsel; member
512 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
517 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1350 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1504 u32 divsel; in dsiclk_rate() local
1507 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()
1508 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1510 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()
1511 divsel in dsiclk_rate()
[all...] |
| /kernel/linux/linux-6.6/drivers/mfd/ |
| H A D | db8500-prcmu.c | 504 u32 divsel; member
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1349 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1503 u32 divsel; in dsiclk_rate() local
1506 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()
1507 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1509 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()
1510 divsel in dsiclk_rate()
[all...] |
| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| H A D | wm9713.c | 741 u32 divsel:1; member
764 pll_div->divsel = 1; in pll_factors()
773 pll_div->divsel = 0; in pll_factors()
834 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
839 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
|
| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| H A D | wm9713.c | 741 u32 divsel:1; member
764 pll_div->divsel = 1; in pll_factors()
773 pll_div->divsel = 0; in pll_factors()
834 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
839 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_display.c | 5644 u32 divsel, phaseinc, auxdiv, phasedir = 0; in lpt_program_iclkip() local
5662 divsel = (desired_divisor / iclk_pi_range) - 2; in lpt_program_iclkip()
5669 if (divsel <= 0x7f) in lpt_program_iclkip()
5674 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & in lpt_program_iclkip()
5680 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", in lpt_program_iclkip()
5681 clock, auxdiv, divsel, phasedir, phaseinc); in lpt_program_iclkip()
5688 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); in lpt_program_iclkip()
5716 u32 divsel, phaseinc, auxdiv; in lpt_get_iclkip() local
5734 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> in lpt_get_iclkip()
5745 desired_divisor = (divsel in lpt_get_iclkip()
[all...] |
Completed in 24 milliseconds