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Help
Searched
refs:divider_reg
(Results
1 - 8
of
8
) sorted by relevance
/kernel/linux/linux-5.10/drivers/clk/
H
A
D
clk-xgene.c
430
void __iomem *
divider_reg
; /* CSR for divider */
member
539
if (pclk->param.
divider_reg
) {
in xgene_clk_recalc_rate()
540
data = xgene_clk_read(pclk->param.
divider_reg
+
in xgene_clk_recalc_rate()
569
if (pclk->param.
divider_reg
) {
in xgene_clk_set_rate()
578
data = xgene_clk_read(pclk->param.
divider_reg
+
in xgene_clk_set_rate()
583
xgene_clk_write(data, pclk->param.
divider_reg
+
in xgene_clk_set_rate()
604
if (pclk->param.
divider_reg
) {
in xgene_clk_round_rate()
681
parameters.
divider_reg
= NULL;
in xgene_devclk_init()
698
parameters.
divider_reg
= map_res;
in xgene_devclk_init()
736
if (parameters.
divider_reg
)
in xgene_devclk_init()
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H
A
D
clk-xgene.c
429
void __iomem *
divider_reg
; /* CSR for divider */
member
538
if (pclk->param.
divider_reg
) {
in xgene_clk_recalc_rate()
539
data = xgene_clk_read(pclk->param.
divider_reg
+
in xgene_clk_recalc_rate()
568
if (pclk->param.
divider_reg
) {
in xgene_clk_set_rate()
577
data = xgene_clk_read(pclk->param.
divider_reg
+
in xgene_clk_set_rate()
582
xgene_clk_write(data, pclk->param.
divider_reg
+
in xgene_clk_set_rate()
603
if (pclk->param.
divider_reg
) {
in xgene_clk_round_rate()
680
parameters.
divider_reg
= NULL;
in xgene_devclk_init()
697
parameters.
divider_reg
= map_res;
in xgene_devclk_init()
735
if (parameters.
divider_reg
)
in xgene_devclk_init()
[all...]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
H
A
D
ap-cpu-clk.c
35
* @
divider_reg
: full integer ratio from PLL frequency to CPU clock frequency
40
unsigned int
divider_reg
;
member
78
.
divider_reg
= AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
112
.
divider_reg
= AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
151
cpu_clkdiv_reg = clk->pll_regs->
divider_reg
+
in ap_cpu_clk_recalc_rate()
167
cpu_clkdiv_reg = clk->pll_regs->
divider_reg
+
in ap_cpu_clk_set_rate()
/kernel/linux/linux-6.6/drivers/clk/mvebu/
H
A
D
ap-cpu-clk.c
34
* @
divider_reg
: full integer ratio from PLL frequency to CPU clock frequency
39
unsigned int
divider_reg
;
member
77
.
divider_reg
= AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
111
.
divider_reg
= AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
150
cpu_clkdiv_reg = clk->pll_regs->
divider_reg
+
in ap_cpu_clk_recalc_rate()
166
cpu_clkdiv_reg = clk->pll_regs->
divider_reg
+
in ap_cpu_clk_set_rate()
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H
A
D
clk-mtk.h
66
uint32_t
divider_reg
;
member
136
.
divider_reg
= _div_reg, \
H
A
D
clk-mtk.c
207
div->reg = base + mc->
divider_reg
;
in mtk_clk_register_composite()
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H
A
D
clk-mtk.h
97
uint32_t
divider_reg
;
member
167
.
divider_reg
= _div_reg, \
H
A
D
clk-mtk.c
275
div->reg = base + mc->
divider_reg
;
in mtk_clk_register_composite()
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