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Searched refs:display_v_start (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_intf.c84 u32 display_v_start, display_v_end; in dpu_hw_intf_setup_timing_engine() local
100 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * in dpu_hw_intf_setup_timing_engine()
117 active_v_start = display_v_start; in dpu_hw_intf_setup_timing_engine()
140 active_v_start = display_v_start; in dpu_hw_intf_setup_timing_engine()
143 display_v_start += p->hsync_pulse_width + p->h_back_porch; in dpu_hw_intf_setup_timing_engine()
182 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); in dpu_hw_intf_setup_timing_engine()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_dsi_encoder.c45 uint32_t display_v_start, display_v_end; in mdp4_dsi_encoder_mode_set() local
66 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
77 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); in mdp4_dsi_encoder_mode_set()
H A Dmdp4_dtv_encoder.c46 uint32_t display_v_start, display_v_end; in mdp4_dtv_encoder_mode_set() local
71 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp4_dtv_encoder_mode_set()
82 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
H A Dmdp4_lcdc_encoder.c221 uint32_t display_v_start, display_v_end; in mdp4_lcdc_encoder_mode_set() local
246 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew; in mdp4_lcdc_encoder_mode_set()
257 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start); in mdp4_lcdc_encoder_mode_set()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_dsi_encoder.c47 uint32_t display_v_start, display_v_end; in mdp4_dsi_encoder_mode_set() local
68 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
79 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); in mdp4_dsi_encoder_mode_set()
H A Dmdp4_dtv_encoder.c46 uint32_t display_v_start, display_v_end; in mdp4_dtv_encoder_mode_set() local
71 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp4_dtv_encoder_mode_set()
82 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
H A Dmdp4_lcdc_encoder.c221 uint32_t display_v_start, display_v_end; in mdp4_lcdc_encoder_mode_set() local
246 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew; in mdp4_lcdc_encoder_mode_set()
257 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start); in mdp4_lcdc_encoder_mode_set()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_intf.c103 u32 display_v_start, display_v_end; in dpu_hw_intf_setup_timing_engine() local
127 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * in dpu_hw_intf_setup_timing_engine()
144 active_v_start = display_v_start; in dpu_hw_intf_setup_timing_engine()
176 display_v_start += p->hsync_pulse_width + p->h_back_porch; in dpu_hw_intf_setup_timing_engine()
181 active_v_start = display_v_start; in dpu_hw_intf_setup_timing_engine()
212 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); in dpu_hw_intf_setup_timing_engine()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_encoder.c40 uint32_t display_v_start, display_v_end; in mdp5_vid_encoder_mode_set() local
89 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_vid_encoder_mode_set()
98 display_v_start += mode->htotal - mode->hsync_start; in mdp5_vid_encoder_mode_set()
112 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); in mdp5_vid_encoder_mode_set()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_encoder.c40 uint32_t display_v_start, display_v_end; in mdp5_vid_encoder_mode_set() local
89 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_vid_encoder_mode_set()
98 display_v_start += mode->htotal - mode->hsync_start; in mdp5_vid_encoder_mode_set()
112 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); in mdp5_vid_encoder_mode_set()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c753 u32 display_v_start, display_v_end; in dp_catalog_panel_tpg_enable() local
763 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * in dp_catalog_panel_tpg_enable()
769 display_v_start += drm_mode->htotal - drm_mode->hsync_start; in dp_catalog_panel_tpg_enable()
793 dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); in dp_catalog_panel_tpg_enable()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c907 u32 display_v_start, display_v_end; in dp_catalog_panel_tpg_enable() local
917 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * in dp_catalog_panel_tpg_enable()
923 display_v_start += drm_mode->htotal - drm_mode->hsync_start; in dp_catalog_panel_tpg_enable()
947 dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); in dp_catalog_panel_tpg_enable()

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