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Searched refs:display_config (Results 1 - 25 of 45) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c302 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data()
309 if (display_config == NULL) in phm_store_dal_configuration_data()
313 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data()
315 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data()
316 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data()
330 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data()
331 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data()
332 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data()
333 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
301 phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, const struct amd_pp_display_configuration *display_config) phm_store_dal_configuration_data() argument
H A Dvega12_hwmgr.c1593 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1594 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1595 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1600 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1601 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1602 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2334 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2335 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2337 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2388 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config in vega12_apply_clocks_adjust_rules()
[all...]
H A Dsmu7_hwmgr.c3022 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3023 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3054 if (hwmgr->display_config->num_display == 0) in smu7_apply_state_adjust_rules()
3057 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3058 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3060 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time); in smu7_apply_state_adjust_rules()
3736 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()
4161 if (hwmgr->display_config->num_display > 1 && in smu7_notify_smc_display_config_after_ps_adjustment()
4162 !hwmgr->display_config->multi_monitor_in_sync) in smu7_notify_smc_display_config_after_ps_adjustment()
4183 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config in smu7_program_display_gap()
[all...]
H A Dvega10_hwmgr.c3279 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3280 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3320 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3323 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3324 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3356 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3422 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
4046 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4047 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4048 !hwmgr->display_config in vega10_notify_smc_display_config_after_ps_adjustment()
[all...]
H A Dvega20_hwmgr.c2347 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2348 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2349 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3660 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3735 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3736 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3738 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3789 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3790 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3797 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config in vega20_apply_clocks_adjust_rules()
[all...]
H A Dsmu10_hwmgr.c193 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
595 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
596 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
711 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
H A Dsmu8_hwmgr.c702 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
760 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
1068 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1069 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1077 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c305 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data()
312 if (display_config == NULL) in phm_store_dal_configuration_data()
316 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data()
318 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data()
319 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data()
333 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data()
334 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data()
335 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data()
336 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
304 phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, const struct amd_pp_display_configuration *display_config) phm_store_dal_configuration_data() argument
H A Dvega12_hwmgr.c1613 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1614 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1615 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1620 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1621 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1622 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2356 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2357 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2359 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2410 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config in vega12_apply_clocks_adjust_rules()
[all...]
H A Dvega20_hwmgr.c2347 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2348 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2349 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3662 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3737 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3738 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3740 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3791 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3792 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3799 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config in vega20_apply_clocks_adjust_rules()
[all...]
H A Dsmu10_hwmgr.c194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
628 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
785 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
H A Dsmu8_hwmgr.c702 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
760 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
1082 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1083 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1091 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
H A Dvega10_hwmgr.c3306 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3307 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3347 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3350 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3351 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3383 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3449 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
4073 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4074 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4075 !hwmgr->display_config in vega10_notify_smc_display_config_after_ps_adjustment()
[all...]
H A Dsmu7_hwmgr.c3355 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3356 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3386 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3387 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3388 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()
3389 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()
3394 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()
3436 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()
4125 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()
4582 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config in smu7_program_display_gap()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-davinci/
H A Dda8xx.h76 (struct vpif_display_config *display_config);
H A Dda850.c333 *display_config) in da850_register_vpif_display()
335 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
332 da850_register_vpif_display(struct vpif_display_config *display_config) da850_register_vpif_display() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c833 smu->display_config = &adev->pm.pm_display_cfg; in smu_sw_init()
1341 const struct amd_pp_display_configuration *display_config) in smu_display_configuration_change()
1349 if (!display_config) in smu_display_configuration_change()
1355 display_config->min_dcef_deep_sleep_set_clk / 100); in smu_display_configuration_change()
1357 for (index = 0; index < display_config->num_path_including_non_display; index++) { in smu_display_configuration_change()
1358 if (display_config->displays[index].controller_id != 0) in smu_display_configuration_change()
1364 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time, in smu_display_configuration_change()
1365 display_config->cpu_cc6_disable, in smu_display_configuration_change()
1366 display_config->cpu_pstate_disable, in smu_display_configuration_change()
1367 display_config in smu_display_configuration_change()
1340 smu_display_configuration_change(struct smu_context *smu, const struct amd_pp_display_configuration *display_config) smu_display_configuration_change() argument
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/include/mach/
H A Dda8xx.h124 (struct vpif_display_config *display_config);
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Ddm646x.c609 void dm646x_setup_vpif(struct vpif_display_config *display_config, in dm646x_setup_vpif() argument
627 vpif_display_dev.dev.platform_data = display_config; in dm646x_setup_vpif()
H A Dda850.c584 *display_config) in da850_register_vpif_display()
586 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
583 da850_register_vpif_display(struct vpif_display_config *display_config) da850_register_vpif_display() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
H A Dhardwaremanager.h431 const struct amd_pp_display_configuration *display_config);
H A Damdgpu_smu.h409 struct amd_pp_display_configuration *display_config; member
766 *display_config);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h428 const struct amd_pp_display_configuration *display_config);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/
H A Damd_powerplay.c57 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1063 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change()
1071 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
1062 pp_display_configuration_change(void *handle, const struct amd_pp_display_configuration *display_config) pp_display_configuration_change() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/
H A Damd_powerplay.c58 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1034 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change()
1041 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
1033 pp_display_configuration_change(void *handle, const struct amd_pp_display_configuration *display_config) pp_display_configuration_change() argument

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