Home
last modified time | relevance | path

Searched refs:dim1 (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dsys_titan.c69 volatile unsigned long *dim0, *dim1, *dim2, *dim3; in titan_update_irq_hw()
85 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
89 if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy; in titan_update_irq_hw()
94 *dim1 = mask1; in titan_update_irq_hw()
99 *dim1; in titan_update_irq_hw()
105 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
68 volatile unsigned long *dim0, *dim1, *dim2, *dim3; titan_update_irq_hw() local
H A Dsys_dp264.c54 volatile unsigned long *dim0, *dim1, *dim2, *dim3; in tsunami_update_irq_hw() local
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
73 if (!cpu_possible(1)) dim1 = &dummy; in tsunami_update_irq_hw()
78 *dim1 = mask1; in tsunami_update_irq_hw()
83 *dim1; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
H A Dcore_tsunami.c402 printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); in tsunami_init_arch()
H A Dcore_titan.c379 printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr); in titan_init_arch()
/kernel/linux/linux-6.6/arch/alpha/kernel/
H A Dsys_titan.c69 volatile unsigned long *dim0, *dim1, *dim2, *dim3; in titan_update_irq_hw()
85 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
89 if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy; in titan_update_irq_hw()
94 *dim1 = mask1; in titan_update_irq_hw()
99 *dim1; in titan_update_irq_hw()
105 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
68 volatile unsigned long *dim0, *dim1, *dim2, *dim3; titan_update_irq_hw() local
H A Dsys_dp264.c54 volatile unsigned long *dim0, *dim1, *dim2, *dim3; in tsunami_update_irq_hw() local
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
73 if (!cpu_possible(1)) dim1 = &dummy; in tsunami_update_irq_hw()
78 *dim1 = mask1; in tsunami_update_irq_hw()
83 *dim1; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
H A Dcore_tsunami.c402 printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); in tsunami_init_arch()
H A Dcore_titan.c379 printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr); in titan_init_arch()
/kernel/linux/linux-5.10/include/linux/dma/
H A Dti-cppi5.h738 * @dim1: Signed dimension for loop level 1
745 s32 dim1; member
754 * @dim1: Signed dimension for loop level 1
764 s32 dim1; member
776 * @dim1: Signed dimension for loop level 1
787 s32 dim1; member
802 * @dim1: Signed dimension for loop level 1 for source
825 s32 dim1; member
/kernel/linux/linux-6.6/include/linux/dma/
H A Dti-cppi5.h739 * @dim1: Signed dimension for loop level 1
746 s32 dim1; member
755 * @dim1: Signed dimension for loop level 1
765 s32 dim1; member
777 * @dim1: Signed dimension for loop level 1
788 s32 dim1; member
803 * @dim1: Signed dimension for loop level 1 for source
826 s32 dim1; member
/kernel/linux/linux-5.10/arch/alpha/include/asm/
H A Dcore_tsunami.h44 tsunami_64 dim1; member
H A Dcore_titan.h45 titan_64 dim1; member
/kernel/linux/linux-6.6/arch/alpha/include/asm/
H A Dcore_tsunami.h44 tsunami_64 dim1; member
H A Dcore_titan.h45 titan_64 dim1; member
/kernel/linux/linux-5.10/drivers/dma/ti/
H A Dk3-udma.c2069 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_slave_sg_tr()
2082 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_slave_sg_tr()
2428 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_dma_cyclic_tr()
2442 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_dma_cyclic_tr()
2635 tr_req[0].dim1 = tr0_cnt0; in udma_prep_dma_memcpy()
/kernel/linux/linux-6.6/drivers/dma/ti/
H A Dk3-udma.c2933 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_slave_sg_tr()
2946 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_slave_sg_tr()
3075 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3091 tr_req[tr_idx].dim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3122 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3137 tr_req[tr_idx].dim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3510 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_dma_cyclic_tr()
3524 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_dma_cyclic_tr()
3728 tr_req[0].dim1 = tr0_cnt0; in udma_prep_dma_memcpy()

Completed in 25 milliseconds