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Searched refs:des0 (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
H A Denh_desc.c19 unsigned int tdes0 = le32_to_cpu(p->des0); in enh_desc_get_tx_status()
123 unsigned int rdes0 = le32_to_cpu(p->basic.des0); in enh_desc_get_ext_status()
188 unsigned int rdes0 = le32_to_cpu(p->des0); in enh_desc_get_rx_status()
262 p->des0 |= cpu_to_le32(RDES0_OWN); in enh_desc_init_rx_desc()
278 p->des0 &= cpu_to_le32(~ETDES0_OWN); in enh_desc_init_tx_desc()
287 return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31; in enh_desc_get_tx_owner()
292 p->des0 |= cpu_to_le32(ETDES0_OWN); in enh_desc_set_tx_owner()
297 p->des0 |= cpu_to_le32(RDES0_OWN); in enh_desc_set_rx_owner()
302 return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29; in enh_desc_get_tx_ls()
307 int ter = (le32_to_cpu(p->des0) in enh_desc_release_tx_desc()
[all...]
H A Dnorm_desc.c19 unsigned int tdes0 = le32_to_cpu(p->des0); in ndesc_get_tx_status()
77 unsigned int rdes0 = le32_to_cpu(p->des0); in ndesc_get_rx_status()
130 p->des0 |= cpu_to_le32(RDES0_OWN); in ndesc_init_rx_desc()
146 p->des0 &= cpu_to_le32(~TDES0_OWN); in ndesc_init_tx_desc()
155 return (le32_to_cpu(p->des0) & TDES0_OWN) >> 31; in ndesc_get_tx_owner()
160 p->des0 |= cpu_to_le32(TDES0_OWN); in ndesc_set_tx_owner()
165 p->des0 |= cpu_to_le32(RDES0_OWN); in ndesc_set_rx_owner()
211 p->des0 |= cpu_to_le32(TDES0_OWN); in ndesc_prepare_tx_desc()
232 return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK) in ndesc_get_rx_frame_len()
245 return (le32_to_cpu(p->des0) in ndesc_get_tx_timestamp_status()
[all...]
H A Ddwxgmac2_descs.c91 ns += le32_to_cpu(p->des0); in dwxgmac2_get_timestamp()
108 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff)) in dwxgmac2_rx_check_timestamp()
137 p->des0 = 0; in dwxgmac2_init_tx_desc()
223 p->des0 = 0; in dwxgmac2_release_tx_desc()
236 p->des0 = 0; in dwxgmac2_set_mss()
244 *addr = le32_to_cpu(p->des0); in dwxgmac2_get_addr()
249 p->des0 = cpu_to_le32(lower_32_bits(addr)); in dwxgmac2_set_addr()
255 p->des0 = 0; in dwxgmac2_clear()
311 p->des0 = 0; in dwxgmac2_set_vlan_tag()
H A Ddwmac4_descs.c221 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */ in dwmac4_wrback_get_tx_timestamp_status()
233 ns = le32_to_cpu(p->des0); in dwmac4_get_timestamp()
243 unsigned int rdes0 = le32_to_cpu(p->des0); in dwmac4_rx_check_timestamp()
305 p->des0 = 0; in dwmac4_rd_init_tx_desc()
394 p->des0 = 0; in dwmac4_release_tx_desc()
420 le32_to_cpu(p->des0), le32_to_cpu(p->des1), in dwmac4_display_ring()
431 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1), in dwmac4_display_ring()
446 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1), in dwmac4_display_ring()
457 p->des0 = 0; in dwmac4_set_mss_ctxt()
465 *addr = le32_to_cpu(p->des0); in dwmac4_get_addr()
[all...]
H A Ddescs_com.h37 p->des0 |= cpu_to_le32(ETDES0_END_RING); in enh_desc_end_tx_desc_on_ring()
39 p->des0 &= cpu_to_le32(~ETDES0_END_RING); in enh_desc_end_tx_desc_on_ring()
98 p->des0 |= cpu_to_le32(ETDES0_SECOND_ADDRESS_CHAINED); in enh_desc_end_tx_desc_on_chain()
H A Ddescs.h159 __le32 des0; member
H A Dstmmac_main.c3130 desc->des0 = cpu_to_le32(curr_addr); in stmmac_tso_allocator()
3264 first->des0 = cpu_to_le32(des); in stmmac_tso_xmit()
4418 le32_to_cpu(ep->basic.des0), in sysfs_display_ring()
4427 le32_to_cpu(p->des0), le32_to_cpu(p->des1), in sysfs_display_ring()
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
H A Denh_desc.c18 unsigned int tdes0 = le32_to_cpu(p->des0); in enh_desc_get_tx_status()
120 unsigned int rdes0 = le32_to_cpu(p->basic.des0); in enh_desc_get_ext_status()
184 unsigned int rdes0 = le32_to_cpu(p->des0); in enh_desc_get_rx_status()
257 p->des0 |= cpu_to_le32(RDES0_OWN); in enh_desc_init_rx_desc()
273 p->des0 &= cpu_to_le32(~ETDES0_OWN); in enh_desc_init_tx_desc()
282 return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31; in enh_desc_get_tx_owner()
287 p->des0 |= cpu_to_le32(ETDES0_OWN); in enh_desc_set_tx_owner()
292 p->des0 |= cpu_to_le32(RDES0_OWN); in enh_desc_set_rx_owner()
297 return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29; in enh_desc_get_tx_ls()
302 int ter = (le32_to_cpu(p->des0) in enh_desc_release_tx_desc()
[all...]
H A Dnorm_desc.c18 unsigned int tdes0 = le32_to_cpu(p->des0); in ndesc_get_tx_status()
73 unsigned int rdes0 = le32_to_cpu(p->des0); in ndesc_get_rx_status()
123 p->des0 |= cpu_to_le32(RDES0_OWN); in ndesc_init_rx_desc()
139 p->des0 &= cpu_to_le32(~TDES0_OWN); in ndesc_init_tx_desc()
148 return (le32_to_cpu(p->des0) & TDES0_OWN) >> 31; in ndesc_get_tx_owner()
153 p->des0 |= cpu_to_le32(TDES0_OWN); in ndesc_set_tx_owner()
158 p->des0 |= cpu_to_le32(RDES0_OWN); in ndesc_set_rx_owner()
204 p->des0 |= cpu_to_le32(TDES0_OWN); in ndesc_prepare_tx_desc()
225 return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK) in ndesc_get_rx_frame_len()
238 return (le32_to_cpu(p->des0) in ndesc_get_tx_timestamp_status()
[all...]
H A Ddwxgmac2_descs.c91 ns += le32_to_cpu(p->des0); in dwxgmac2_get_timestamp()
108 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff)) in dwxgmac2_rx_check_timestamp()
137 p->des0 = 0; in dwxgmac2_init_tx_desc()
223 p->des0 = 0; in dwxgmac2_release_tx_desc()
236 p->des0 = 0; in dwxgmac2_set_mss()
244 p->des0 = cpu_to_le32(lower_32_bits(addr)); in dwxgmac2_set_addr()
250 p->des0 = 0; in dwxgmac2_clear()
306 p->des0 = 0; in dwxgmac2_set_vlan_tag()
H A Ddwmac4_descs.c217 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */ in dwmac4_wrback_get_tx_timestamp_status()
229 ns = le32_to_cpu(p->des0); in dwmac4_get_timestamp()
239 unsigned int rdes0 = le32_to_cpu(p->des0); in dwmac4_rx_check_timestamp()
301 p->des0 = 0; in dwmac4_rd_init_tx_desc()
390 p->des0 = 0; in dwmac4_release_tx_desc()
416 le32_to_cpu(p->des0), le32_to_cpu(p->des1), in dwmac4_display_ring()
427 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1), in dwmac4_display_ring()
442 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1), in dwmac4_display_ring()
453 p->des0 = 0; in dwmac4_set_mss_ctxt()
461 p->des0 in dwmac4_set_addr()
[all...]
H A Ddescs_com.h37 p->des0 |= cpu_to_le32(ETDES0_END_RING); in enh_desc_end_tx_desc_on_ring()
39 p->des0 &= cpu_to_le32(~ETDES0_END_RING); in enh_desc_end_tx_desc_on_ring()
98 p->des0 |= cpu_to_le32(ETDES0_SECOND_ADDRESS_CHAINED); in enh_desc_end_tx_desc_on_chain()
H A Ddescs.h159 __le32 des0; member
H A Dstmmac_main.c4060 desc->des0 = cpu_to_le32(curr_addr); in stmmac_tso_allocator()
4220 first->des0 = cpu_to_le32(des); in stmmac_tso_xmit()
6170 le32_to_cpu(ep->basic.des0), in sysfs_display_ring()
6179 le32_to_cpu(p->des0), le32_to_cpu(p->des1), in sysfs_display_ring()
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Ddw_mmc.c64 u32 des0; /* Control Descriptor */ member
85 __le32 des0; /* Control Descriptor */ member
517 p->des0 = 0; in dw_mci_idmac_init()
526 p->des0 = IDMAC_DES0_ER; in dw_mci_idmac_init()
540 p->des0 = 0; in dw_mci_idmac_init()
546 p->des0 = cpu_to_le32(IDMAC_DES0_ER); in dw_mci_idmac_init()
602 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc64()
611 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | in dw_mci_prepare_desc64()
630 desc_first->des0 |= IDMAC_DES0_FD; in dw_mci_prepare_desc64()
633 desc_last->des0 in dw_mci_prepare_desc64()
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Ddw_mmc.c66 u32 des0; /* Control Descriptor */ member
87 __le32 des0; /* Control Descriptor */ member
522 p->des0 = 0; in dw_mci_idmac_init()
531 p->des0 = IDMAC_DES0_ER; in dw_mci_idmac_init()
545 p->des0 = 0; in dw_mci_idmac_init()
551 p->des0 = cpu_to_le32(IDMAC_DES0_ER); in dw_mci_idmac_init()
607 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc64()
616 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | in dw_mci_prepare_desc64()
635 desc_first->des0 |= IDMAC_DES0_FD; in dw_mci_prepare_desc64()
638 desc_last->des0 in dw_mci_prepare_desc64()
[all...]

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