| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | skl_watermark.c | 779 struct skl_ddb_entry *ddb_y) in skl_ddb_get_hw_plane_state()
797 skl_ddb_entry_init_from_hw(ddb_y, val); in skl_ddb_get_hw_plane_state()
802 struct skl_ddb_entry *ddb_y) in skl_pipe_ddb_get_hw_state()
819 &ddb_y[plane_id]); in skl_pipe_ddb_get_hw_state()
1428 const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb) in skl_check_nv12_wm_level()
1430 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || in skl_check_nv12_wm_level()
1577 struct skl_ddb_entry *ddb_y = in skl_crtc_allocate_plane_ddb() local
1587 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], in skl_crtc_allocate_plane_ddb()
1608 const struct skl_ddb_entry *ddb_y = in skl_crtc_allocate_plane_ddb() local
1617 ddb_y, dd in skl_crtc_allocate_plane_ddb()
775 skl_ddb_get_hw_plane_state(struct drm_i915_private *i915, const enum pipe pipe, const enum plane_id plane_id, struct skl_ddb_entry *ddb, struct skl_ddb_entry *ddb_y) skl_ddb_get_hw_plane_state() argument
800 skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb, struct skl_ddb_entry *ddb_y) skl_pipe_ddb_get_hw_state() argument
1427 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm, const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb) skl_check_nv12_wm_level() argument
1636 const struct skl_ddb_entry *ddb_y = skl_crtc_allocate_plane_ddb() local
2388 const struct skl_ddb_entry *ddb_y = skl_write_plane_wm() local
3021 struct skl_ddb_entry *ddb_y = skl_wm_get_hw_state() local
3141 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; intel_wm_state_verify() member
[all...] |
| H A D | intel_atomic_plane.c | 725 struct skl_ddb_entry ddb_y[I915_MAX_PLANES], in skl_next_plane_to_commit()
747 ddb_y, I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
752 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
835 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; in skl_crtc_planes_update_arm() local
841 memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y, in skl_crtc_planes_update_arm()
844 while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) { in skl_crtc_planes_update_arm()
722 skl_next_plane_to_commit(struct intel_atomic_state *state, struct intel_crtc *crtc, struct skl_ddb_entry ddb[I915_MAX_PLANES], struct skl_ddb_entry ddb_y[I915_MAX_PLANES], unsigned int *update_mask) skl_next_plane_to_commit() argument
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | intel_pm.h | 40 struct skl_ddb_entry *ddb_y,
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| H A D | intel_pm.c | 4302 struct skl_ddb_entry *ddb_y, in skl_ddb_get_hw_plane_state()
4311 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); in skl_ddb_get_hw_plane_state()
4325 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); in skl_ddb_get_hw_plane_state()
4334 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); in skl_ddb_get_hw_plane_state()
4340 struct skl_ddb_entry *ddb_y, in skl_pipe_ddb_get_hw_state()
4357 &ddb_y[plane_id], in skl_pipe_ddb_get_hw_state()
5654 const struct skl_ddb_entry *ddb_y = in skl_write_plane_wm() local
5672 PLANE_BUF_CFG(pipe, plane_id), ddb_y); in skl_write_plane_wm()
5677 swap(ddb_y, ddb_uv); in skl_write_plane_wm()
5680 PLANE_BUF_CFG(pipe, plane_id), ddb_y); in skl_write_plane_wm()
4299 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, const enum pipe pipe, const enum plane_id plane_id, struct skl_ddb_entry *ddb_y, struct skl_ddb_entry *ddb_uv) skl_ddb_get_hw_plane_state() argument
4339 skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb_y, struct skl_ddb_entry *ddb_uv) skl_pipe_ddb_get_hw_state() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_display.c | 14086 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; in verify_wm_state() member
14106 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); in verify_wm_state()
14157 hw_ddb_entry = &hw->ddb_y[plane]; in verify_wm_state()
14214 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR]; in verify_wm_state()
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