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Searched refs:dcfclk (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c487 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp() local
491 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
492 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()
499 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
504 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg() local
416 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
421 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_fpu_calculate_wm_and_dlg()
422 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
425 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
451 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h53 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
60 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
129 uint32_t dcfclk; member
143 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
149 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
158 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
165 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
171 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
153 uint32_t dcfclk; member
168 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
174 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
183 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
190 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
196 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/calcs/
H A Ddcn_calc_auto.c1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1226 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1234 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1235 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1237 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1239 v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1241 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1242 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1243 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1245 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
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H A Ddcn_calcs.c491 input.clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
575 v->dcfclk = v->dcfclkv_nom0p8;
596 v->dcfclk = v->dcfclkv_max0p9;
616 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
1178 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); in dcn_validate_bandwidth()
1448 /*find that level conresponding dcfclk*/ in dcn_find_dcfclk_suits_all()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calc_auto.c1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1226 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1234 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1235 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1237 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1239 v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1241 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1242 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1243 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1245 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
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H A Ddcn_calcs.c494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
577 v->dcfclk = v->dcfclkv_nom0p8;
598 v->dcfclk = v->dcfclkv_max0p9;
618 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
1163 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); in dcn_validate_bandwidth()
1429 /*find that level conresponding dcfclk*/ in dcn_find_dcfclk_suits_all()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c275 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in rn_dump_clk_registers()
301 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", in rn_dump_clk_registers()
302 regs_and_bypass->dcfclk, in rn_dump_clk_registers()
336 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", in rn_dump_clk_registers()
441 /* dcfclk wil be used to select WM*/ in build_watermark_ranges()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c315 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in rn_dump_clk_registers()
341 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", in rn_dump_clk_registers()
342 regs_and_bypass->dcfclk, in rn_dump_clk_registers()
376 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", in rn_dump_clk_registers()
470 /* dcfclk wil be used to select WM*/ in build_watermark_ranges()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c247 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in vg_dump_clk_registers()
273 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", in vg_dump_clk_registers()
274 regs_and_bypass->dcfclk, in vg_dump_clk_registers()
308 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", in vg_dump_clk_registers()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
H A Ddcn_calcs.h213 float dcfclk; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/
H A Ddcn_calcs.h213 float dcfclk; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c514 !dc->work_arounds.clock_update_disable_mask.dcfclk) { in dcn32_update_clocks()
730 //Get dcfclk in khz in dcn32_dump_clk_registers()
731 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2224 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_calculate_wm_and_dlg_fp() local
2228 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_calculate_wm_and_dlg_fp()
2229 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2232 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2258 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2523 // Calculate optimal dcfclk for each uclk in dcn30_update_bw_bounding_box()
2534 // Calculate optimal uclk for each dcfclk sta target in dcn30_update_bw_bounding_box()
2547 // create the final dcfclk and uclk table in dcn30_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c550 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn32_set_phantom_stream_timing() local
578 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_set_phantom_stream_timing()
1965 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu() local
2077 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2079 dcfclk = 615; //DCFCLK Vmin_lv in dcn32_calculate_wm_and_dlg_fpu()
2082 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_calculate_wm_and_dlg_fpu()
2112 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2114 dcfclk = 615; //DCFCLK Vmin_lv in dcn32_calculate_wm_and_dlg_fpu()
2117 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_calculate_wm_and_dlg_fpu()
2840 // Calculate optimal dcfclk fo in dcn32_update_bw_bounding_box_fpu()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A Ddc.h288 uint8_t dcfclk : 1; member

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