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Searched refs:cp_int_cntl (Results 1 - 18 of 18) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c3237 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local
3241 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3242 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3243 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3246 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3247 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3248 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3259 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local
3263 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3264 cp_int_cntl in gfx_v6_0_set_compute_eop_interrupt_state()
3300 u32 cp_int_cntl; gfx_v6_0_set_priv_reg_fault_state() local
3325 u32 cp_int_cntl; gfx_v6_0_set_priv_inst_fault_state() local
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H A Dgfx_v7_0.c4723 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
4727 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4728 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4729 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4732 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4733 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4734 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4797 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
4801 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4802 cp_int_cntl in gfx_v7_0_set_priv_reg_fault_state()
4822 u32 cp_int_cntl; gfx_v7_0_set_priv_inst_fault_state() local
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H A Dgfx_v10_0.c8213 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
8234 cp_int_cntl = RREG32(cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8235 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8237 WREG32(cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8240 cp_int_cntl = RREG32(cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8241 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8243 WREG32(cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c3202 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local
3206 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3207 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3208 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3212 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3213 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3224 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local
3228 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3229 cp_int_cntl in gfx_v6_0_set_compute_eop_interrupt_state()
3265 u32 cp_int_cntl; gfx_v6_0_set_priv_reg_fault_state() local
3290 u32 cp_int_cntl; gfx_v6_0_set_priv_inst_fault_state() local
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H A Dgfx_v7_0.c4663 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
4667 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4668 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4669 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4672 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4673 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4674 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4737 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
4741 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4742 cp_int_cntl in gfx_v7_0_set_priv_reg_fault_state()
4762 u32 cp_int_cntl; gfx_v7_0_set_priv_inst_fault_state() local
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H A Dgfx_v11_0.c5719 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v11_0_set_gfx_eop_interrupt_state() local
5740 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
5741 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
5743 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
5745 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5748 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
5749 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING in gfx_v11_0_set_gfx_eop_interrupt_state()
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H A Dgfx_v10_0.c8766 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
8787 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8788 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8790 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8793 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8796 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dni.h32 int ring, u32 cp_int_cntl);
H A Dr600.c3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3821 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
H A Devergreen.c4496 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4527 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4540 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4541 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4564 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4568 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
H A Dni.c1380 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup()
1383 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
1379 cayman_cp_int_cntl_setup(struct radeon_device *rdev, int ring, u32 cp_int_cntl) cayman_cp_int_cntl_setup() argument
H A Dsi.c6052 u32 cp_int_cntl; in si_irq_set() local
6070 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6082 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6102 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
H A Dcik.c7017 u32 cp_int_cntl; in cik_irq_set() local
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Devergreen.c217 int ring, u32 cp_int_cntl);
4494 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4525 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4538 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4539 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4562 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4566 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
H A Dr600.c3766 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3824 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3825 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3876 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
H A Dni.c1393 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup()
1396 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
1392 cayman_cp_int_cntl_setup(struct radeon_device *rdev, int ring, u32 cp_int_cntl) cayman_cp_int_cntl_setup() argument
H A Dsi.c6057 u32 cp_int_cntl; in si_irq_set() local
6075 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6087 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6107 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
H A Dcik.c7028 u32 cp_int_cntl; in cik_irq_set() local
7048 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7050 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7074 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7228 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()

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