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Searched refs:cp_hqd_pq_control (Results 1 - 25 of 41) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_cik.c193 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
197 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
205 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
215 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
319 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
328 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
H A Dkfd_mqd_manager_v9.c222 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
223 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
224 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
263 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
345 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_vi.c177 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | in __update_mqd()
180 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
181 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in __update_mqd()
224 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in __update_mqd()
308 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v10.c171 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
172 m->cp_hqd_pq_control |= in update_mqd()
174 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
212 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
289 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v11.c224 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
225 m->cp_hqd_pq_control |= in update_mqd()
227 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
228 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
266 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
372 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v10.c170 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
171 m->cp_hqd_pq_control |= in update_mqd()
173 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
174 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
212 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
318 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_cik.c179 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
183 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
191 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
201 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
342 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
351 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
H A Dkfd_mqd_manager_v9.c246 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
247 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
248 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
292 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
414 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
535 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in init_mqd_hiq_v9_4_3()
541 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; in init_mqd_hiq_v9_4_3()
657 m->cp_hqd_pq_control &= in init_mqd_v9_4_3()
695 m->cp_hqd_pq_control in update_mqd_v9_4_3()
[all...]
H A Dkfd_mqd_manager_vi.c178 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | in __update_mqd()
181 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
182 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in __update_mqd()
225 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in __update_mqd()
329 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/
H A Dcik_structs.h96 uint32_t cp_hqd_pq_control; member
H A Dvi_structs.h305 uint32_t cp_hqd_pq_control; member
H A Dv9_structs.h305 uint32_t cp_hqd_pq_control; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/
H A Dcik_structs.h96 uint32_t cp_hqd_pq_control; member
H A Dvi_structs.h305 uint32_t cp_hqd_pq_control; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v10_1.c673 mqd->cp_hqd_pq_control = tmp; in mes_v10_1_mqd_init()
764 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v10_1_queue_init_register()
H A Dgfx_v7_0.c2846 u32 cp_hqd_pq_control; member
2959 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2960 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2964 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2966 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2969 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2972 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2976 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
H A Damdgpu_amdkfd_gfx_v10.c269 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
H A Damdgpu_amdkfd_gfx_v9.c280 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_hqd_load()
H A Damdgpu_amdkfd_gfx_v10_3.c254 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v10_3()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c330 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_4_3_hqd_load()
H A Dgfx_v7_0.c2778 u32 cp_hqd_pq_control; member
2891 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2892 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2896 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2898 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2901 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2904 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2908 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
H A Dmes_v11_0.c778 mqd->cp_hqd_pq_control = tmp; in mes_v11_0_mqd_init()
853 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
H A Dmes_v10_1.c701 mqd->cp_hqd_pq_control = tmp; in mes_v10_1_mqd_init()
778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
H A Damdgpu_amdkfd_gfx_v10_3.c240 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c254 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()

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