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Searched refs:counter_config (Results 1 - 7 of 7) sorted by relevance

/kernel/linux/linux-5.10/drivers/oprofile/
H A Doprofile_perf.c29 static struct op_counter_config *counter_config; variable
55 * settings in counter_config. Attributes are created as `pinned' events and
65 attr = &counter_config[i].attr; in op_perf_setup()
69 attr->config = counter_config[i].event; in op_perf_setup()
70 attr->sample_period = counter_config[i].count; in op_perf_setup()
79 if (!counter_config[event].enabled || per_cpu(perf_events, cpu)[event]) in op_create_counter()
82 pevent = perf_event_create_kernel_counter(&counter_config[event].attr, in op_create_counter()
152 oprofilefs_create_ulong(dir, "enabled", &counter_config[i].enabled); in oprofile_perf_create_files()
153 oprofilefs_create_ulong(dir, "event", &counter_config[i].event); in oprofile_perf_create_files()
154 oprofilefs_create_ulong(dir, "count", &counter_config[ in oprofile_perf_create_files()
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/kernel/linux/linux-5.10/arch/x86/oprofile/
H A Dnmi_int.c38 struct op_counter_config counter_config[OP_MAX_COUNTER]; variable
43 struct op_counter_config *counter_config) in op_x86_get_ctrl()
46 u16 event = (u16)counter_config->event; in op_x86_get_ctrl()
49 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; in op_x86_get_ctrl()
50 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; in op_x86_get_ctrl()
51 val |= (counter_config->unit_mask & 0xFF) << 8; in op_x86_get_ctrl()
52 counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV | in op_x86_get_ctrl()
55 val |= counter_config->extra; in op_x86_get_ctrl()
190 if (counter_config[i].enabled) { in nmi_cpu_setup_mux()
191 multiplex[i].saved = -(u64)counter_config[ in nmi_cpu_setup_mux()
42 op_x86_get_ctrl(struct op_x86_model_spec const *model, struct op_counter_config *counter_config) op_x86_get_ctrl() argument
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H A Dop_model_p4.c491 if (!counter_config[i].enabled) in p4_fill_in_addresses()
521 if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) { in pmc_setup_one_p4_counter()
524 counter_config[ctr].event); in pmc_setup_one_p4_counter()
528 ev = &(p4_events[counter_config[ctr].event - 1]); in pmc_setup_one_p4_counter()
537 ESCR_SET_USR_0(escr, counter_config[ctr].user); in pmc_setup_one_p4_counter()
538 ESCR_SET_OS_0(escr, counter_config[ctr].kernel); in pmc_setup_one_p4_counter()
540 ESCR_SET_USR_1(escr, counter_config[ctr].user); in pmc_setup_one_p4_counter()
541 ESCR_SET_OS_1(escr, counter_config[ctr].kernel); in pmc_setup_one_p4_counter()
544 ESCR_SET_EVENT_MASK(escr, counter_config[ct in pmc_setup_one_p4_counter()
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H A Dop_model_ppro.c61 if (!counter_config[i].enabled) in ppro_fill_in_addresses()
113 if (counter_config[i].enabled && msrs->counters[i].addr) { in ppro_setup_ctrs()
114 reset_value[i] = counter_config[i].count; in ppro_setup_ctrs()
118 val |= op_x86_get_ctrl(model, &counter_config[i]); in ppro_setup_ctrs()
H A Dop_model_amd.c281 val |= op_x86_get_ctrl(model, &counter_config[virt]); in op_mux_switch_ctrl()
323 if (!counter_config[i].enabled) in op_amd_fill_in_addresses()
341 if (counter_config[i].enabled in op_amd_setup_ctrs()
343 reset_value[i] = counter_config[i].count; in op_amd_setup_ctrs()
376 val |= op_x86_get_ctrl(model, &counter_config[virt]); in op_amd_setup_ctrs()
H A Dop_counter.h28 extern struct op_counter_config counter_config[];
H A Dop_x86_model.h80 struct op_counter_config *counter_config);

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