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Searched refs:coresight_timeout (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A Dcoresight-tpiu.c91 coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); in tpiu_disable_hw()
93 coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); in tpiu_disable_hw()
H A Dcoresight-tmc-core.c37 if (coresight_timeout(drvdata->base, in tmc_wait_for_tmcready()
54 if (coresight_timeout(drvdata->base, in tmc_flush_and_stop()
H A Dcoresight-etb10.c266 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { in __etb_disable_hw()
274 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { in __etb_disable_hw()
H A Dcoresight-etm4x-core.c124 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) in etm4_enable_hw()
215 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) in etm4_enable_hw()
506 if (coresight_timeout(drvdata->base, TRCSTATR, in etm4_disable_hw()
1173 if (coresight_timeout(drvdata->base, TRCSTATR, in etm4_cpu_save()
1263 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { in etm4_cpu_save()
H A Dcoresight-catu.c404 return coresight_timeout(drvdata->base, in catu_wait_for_ready()
H A Dcoresight-core.c1411 * coresight_timeout - loop until a bit has changed to a specific state.
1421 int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) in coresight_timeout() function
1449 EXPORT_SYMBOL_GPL(coresight_timeout); variable
H A Dcoresight-stm.c273 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0); in stm_disable()
/kernel/linux/linux-5.10/include/linux/
H A Dcoresight.h334 extern int coresight_timeout(void __iomem *addr, u32 offset,
353 static inline int coresight_timeout(void __iomem *addr, u32 offset, in coresight_timeout() function
/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-tpiu.c90 coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); in tpiu_disable_hw()
92 coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); in tpiu_disable_hw()
H A Dcoresight-tmc-core.c40 if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { in tmc_wait_for_tmcready()
60 if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { in tmc_flush_and_stop()
H A Dcoresight-etb10.c268 if (coresight_timeout(csa, ETB_FFCR, ETB_FFCR_BIT, 0)) { in __etb_disable_hw()
276 if (coresight_timeout(csa, ETB_FFSR, ETB_FFSR_BIT, 1)) { in __etb_disable_hw()
H A Dcoresight-etm4x-core.c433 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) in etm4_enable_hw()
526 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) in etm4_enable_hw()
907 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) in etm4_disable_hw()
1673 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { in __etm4_cpu_save()
1765 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { in __etm4_cpu_save()
H A Dcoresight-catu.c395 return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1); in catu_wait_for_ready()
H A Dcoresight-core.c1468 * coresight_timeout - loop until a bit has changed to a specific register
1478 int coresight_timeout(struct csdev_access *csa, u32 offset, in coresight_timeout() function
1507 EXPORT_SYMBOL_GPL(coresight_timeout); variable
H A Dcoresight-stm.c275 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0); in stm_disable()
/kernel/linux/linux-6.6/include/linux/
H A Dcoresight.h576 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
608 static inline int coresight_timeout(struct csdev_access *csa, u32 offset, in coresight_timeout() function

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