| /kernel/linux/linux-6.6/arch/arm/mach-s3c/ |
| H A D | gpio-samsung.c | 406 unsigned con_offset = offset; in samsung_gpiolib_4bit2_output() local
408 if (con_offset > 7) in samsung_gpiolib_4bit2_output()
409 con_offset -= 8; in samsung_gpiolib_4bit2_output()
414 con &= ~(0xf << con_4bit_shift(con_offset)); in samsung_gpiolib_4bit2_output()
415 con |= 0x1 << con_4bit_shift(con_offset); in samsung_gpiolib_4bit2_output()
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| H A D | gpio-samsung.c | 589 unsigned con_offset = offset; in samsung_gpiolib_4bit2_output() local
591 if (con_offset > 7) in samsung_gpiolib_4bit2_output()
592 con_offset -= 8; in samsung_gpiolib_4bit2_output()
597 con &= ~(0xf << con_4bit_shift(con_offset)); in samsung_gpiolib_4bit2_output()
598 con |= 0x1 << con_4bit_shift(con_offset); in samsung_gpiolib_4bit2_output()
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| H A D | clk.h | 243 * @con_offset: offset of the register for configuring the PLL.
252 int con_offset; member
265 .con_offset = _con, \
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| H A D | clk-pll.c | 1387 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| H A D | clk.h | 244 * @con_offset: offset of the register for configuring the PLL.
253 int con_offset; member
266 .con_offset = _con, \
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| H A D | clk-pll.c | 1399 pll->con_reg = ctx->reg_base + pll_clk->con_offset; in _samsung_clk_register_pll()
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| H A D | clk.h | 266 * @con_offset: offset of the register for configuring the PLL.
284 int con_offset; member
304 .con_offset = _con, \
315 u8 num_parents, int con_offset, int grf_lock_offset,
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| H A D | clk-pll.c | 852 u8 num_parents, int con_offset, int grf_lock_offset, in rockchip_clk_register_pll()
967 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
849 rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, unsigned long flags, u8 clk_pll_flags) rockchip_clk_register_pll() argument
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| H A D | clk.c | 426 list->con_offset, grf_lock_offset, in rockchip_clk_register_plls()
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| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| H A D | clk.h | 383 * @con_offset: offset of the register for configuring the PLL.
401 int con_offset; member
421 .con_offset = _con, \
432 u8 num_parents, int con_offset, int grf_lock_offset,
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| H A D | clk-pll.c | 1059 u8 num_parents, int con_offset, int grf_lock_offset, in rockchip_clk_register_pll()
1183 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
1056 rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, unsigned long flags, u8 clk_pll_flags) rockchip_clk_register_pll() argument
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| H A D | clk.c | 417 list->con_offset, grf_lock_offset, in rockchip_clk_register_plls()
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