Searched refs:code_dma_base1 (Results 1 - 8 of 8) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | gm20b.c | 40 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_gr_acr_bld_patch()
42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | gm20b.c | 40 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_gr_acr_bld_patch()
42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvfw/ |
| H A D | flcn.h | 18 u32 code_dma_base1; member
55 u32 code_dma_base1; member
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/include/nvfw/ |
| H A D | flcn.h | 18 u32 code_dma_base1; member
55 u32 code_dma_base1; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| H A D | gm20b.c | 82 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_pmu_acr_bld_patch()
84 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
114 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/nvfw/ |
| H A D | flcn.c | 39 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in loader_config_dump()
82 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in flcn_bl_dmem_desc_dump()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/nvfw/ |
| H A D | flcn.c | 39 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in loader_config_dump()
82 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in flcn_bl_dmem_desc_dump()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| H A D | gm20b.c | 72 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_pmu_acr_bld_patch()
74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
104 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
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