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Searched refs:clk_phase_in (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsdhci-of-arasan.c150 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
160 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; member
1212 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
1234 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
1240 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1278 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1290 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1301 clk_data->clk_phase_in[i] = versal_net_iclk_phase[i]; in arasan_dt_parse_clk_phases()
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci-of-arasan.c114 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
124 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; member
1003 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
1023 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
1029 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1067 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1079 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()

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