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Searched refs:clk_csr (Results 1 - 25 of 26) sorted by relevance

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/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_mdio.c100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()
183 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write()
289 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read_c22()
329 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read_c45()
389 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write_c22()
430 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write_c45()
H A Dstmmac_pci.c24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
77 plat->clk_csr = 5; in snps_gmac5_default_data()
H A Dstmmac_platform.c445 /* Default to get clk_csr from stmmac_clk_csr_set(), in stmmac_probe_config_dt()
446 * or get clk_csr from device tree. in stmmac_probe_config_dt()
448 plat->clk_csr = -1; in stmmac_probe_config_dt()
449 if (of_property_read_u32(np, "snps,clk-csr", &plat->clk_csr)) in stmmac_probe_config_dt()
450 of_property_read_u32(np, "clk_csr", &plat->clk_csr); in stmmac_probe_config_dt()
H A Ddwmac-loongson.c14 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
H A Dstmmac_main.c295 * If a specific clk_csr value is passed from the platform
307 /* Platform provided default clk_csr would be assumed valid in stmmac_clk_csr_set()
314 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set()
316 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set()
318 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set()
320 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set()
322 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set()
324 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set()
326 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set()
331 priv->clk_csr in stmmac_clk_csr_set()
[all...]
H A Dstmmac.h259 int clk_csr; member
H A Ddwmac-intel.c419 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
456 plat->clk_csr = 5; in intel_mgbe_common_data()
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_mdio.c118 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()
186 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write()
241 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read()
310 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write()
H A Dstmmac_pci.c24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
77 plat->clk_csr = 5; in snps_gmac5_default_data()
H A Dstmmac_main.c229 * If a specific clk_csr value is passed from the platform
241 /* Platform provided default clk_csr would be assumed valid in stmmac_clk_csr_set()
248 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set()
250 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set()
252 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set()
254 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set()
256 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set()
258 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set()
260 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set()
265 priv->clk_csr in stmmac_clk_csr_set()
[all...]
H A Ddwmac-loongson.c22 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
H A Dstmmac.h202 int clk_csr; member
H A Ddwmac-intel.c206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
241 plat->clk_csr = 5; in intel_mgbe_common_data()
H A Dstmmac_platform.c444 /* Default to get clk_csr from stmmac_clk_crs_set(), in stmmac_probe_config_dt()
445 * or get clk_csr from device tree. in stmmac_probe_config_dt()
447 plat->clk_csr = -1; in stmmac_probe_config_dt()
448 of_property_read_u32(np, "clk_csr", &plat->clk_csr); in stmmac_probe_config_dt()
/kernel/linux/linux-5.10/include/linux/
H A Dsxgbe_platform.h46 int clk_csr; member
H A Dstmmac.h158 int clk_csr; member
/kernel/linux/linux-6.6/include/linux/
H A Dsxgbe_platform.h46 int clk_csr; member
H A Dstmmac.h251 int clk_csr; member
/kernel/linux/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c176 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()
178 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()
180 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()
182 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()
184 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()
186 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()
2154 /* If a specific clk_csr value is passed from the platform in sxgbe_drv_probe()
2160 if (!priv->plat->clk_csr) in sxgbe_drv_probe()
2163 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
[all...]
H A Dsxgbe_mdio.c48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
H A Dsxgbe_common.h489 int clk_csr; member
/kernel/linux/linux-6.6/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c176 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()
178 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()
180 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()
182 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()
184 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()
186 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()
2157 /* If a specific clk_csr value is passed from the platform in sxgbe_drv_probe()
2163 if (!priv->plat->clk_csr) in sxgbe_drv_probe()
2166 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
[all...]
H A Dsxgbe_common.h489 int clk_csr; member
H A Dsxgbe_mdio.c48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
H A Dqat_hal.c446 unsigned int clk_csr; in qat_hal_clr_reset() local
462 clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE); in qat_hal_clr_reset()
463 clk_csr |= handle->hal_handle->ae_mask << 0; in qat_hal_clr_reset()
464 clk_csr |= handle->hal_handle->slice_mask << 20; in qat_hal_clr_reset()
465 SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); in qat_hal_clr_reset()

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