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Searched refs:chg_pid (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-6.6/drivers/clk/at91/
H A Dsama5d2.c131 int chg_pid; member
133 { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
134 { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
135 { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
136 { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
137 { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
138 { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
139 { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
140 { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
141 { .n = "uart3_gclk", .id = 27, .chg_pid
[all...]
H A Dclk-generated.c32 int chg_pid; member
152 if (gck->chg_pid == i) in clk_generated_determine_rate()
186 if (gck->chg_pid < 0) in clk_generated_determine_rate()
189 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid); in clk_generated_determine_rate()
325 int chg_pid) in at91_clk_register_generated()
347 if (chg_pid >= 0) in at91_clk_register_generated()
355 gck->chg_pid = chg_pid; in at91_clk_register_generated()
319 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, struct clk_hw **parent_hws, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) at91_clk_register_generated() argument
H A Dclk-peripheral.c42 int chg_pid; member
299 if (periph->chg_pid < 0) in clk_sam9x5_peripheral_determine_rate()
303 parent = clk_hw_get_parent_by_index(hw, periph->chg_pid); in clk_sam9x5_peripheral_determine_rate()
453 int chg_pid, unsigned long flags) in at91_clk_register_sam9x5_peripheral()
474 if (chg_pid < 0) { in at91_clk_register_sam9x5_peripheral()
491 periph->chg_pid = chg_pid; in at91_clk_register_sam9x5_peripheral()
448 at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, struct clk_hw *parent_hw, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags) at91_clk_register_sam9x5_peripheral() argument
H A Dclk-master.c36 int chg_pid; member
618 if (master->chg_pid < 0) in clk_sama7g5_master_determine_rate()
621 parent = clk_hw_get_parent_by_index(hw, master->chg_pid); in clk_sama7g5_master_determine_rate()
818 bool critical, int chg_pid) in at91_clk_sama7g5_register_master()
843 if (chg_pid >= 0) in at91_clk_sama7g5_register_master()
851 master->chg_pid = chg_pid; in at91_clk_sama7g5_register_master()
812 at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, struct clk_hw **parent_hws, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) at91_clk_sama7g5_register_master() argument
H A Dpmc.h149 const struct clk_range *range, int chg_pid);
198 int chg_pid);
210 int chg_pid, unsigned long flags);
H A Ddt-compat.c153 int chg_pid = INT_MIN; in of_sama5d2_clk_generated_setup() local
170 chg_pid = GCK_INDEX_DT_AUDIO_PLL; in of_sama5d2_clk_generated_setup()
176 chg_pid); in of_sama5d2_clk_generated_setup()
/kernel/linux/linux-5.10/drivers/clk/at91/
H A Dsama5d2.c119 int chg_pid; member
121 { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
122 { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
123 { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
124 { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
125 { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
126 { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, },
127 { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, },
128 { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, },
129 { .n = "i2s1_gclk", .id = 55, .chg_pid
[all...]
H A Dclk-generated.c31 int chg_pid; member
142 if (gck->chg_pid == i) in clk_generated_determine_rate()
176 if (gck->chg_pid < 0) in clk_generated_determine_rate()
179 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid); in clk_generated_determine_rate()
293 int chg_pid) in at91_clk_register_generated()
309 if (chg_pid >= 0) in at91_clk_register_generated()
317 gck->chg_pid = chg_pid; in at91_clk_register_generated()
288 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) at91_clk_register_generated() argument
H A Dclk-master.c42 int chg_pid; member
231 if (master->chg_pid < 0) in clk_sama7g5_master_determine_rate()
234 parent = clk_hw_get_parent_by_index(hw, master->chg_pid); in clk_sama7g5_master_determine_rate()
395 bool critical, int chg_pid) in at91_clk_sama7g5_register_master()
417 if (chg_pid >= 0) in at91_clk_sama7g5_register_master()
425 master->chg_pid = chg_pid; in at91_clk_sama7g5_register_master()
390 at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) at91_clk_sama7g5_register_master() argument
H A Dclk-peripheral.c41 int chg_pid; member
288 if (periph->chg_pid < 0) in clk_sam9x5_peripheral_determine_rate()
292 parent = clk_hw_get_parent_by_index(hw, periph->chg_pid); in clk_sam9x5_peripheral_determine_rate()
419 int chg_pid) in at91_clk_register_sam9x5_peripheral()
436 if (chg_pid < 0) { in at91_clk_register_sam9x5_peripheral()
454 periph->chg_pid = chg_pid; in at91_clk_register_sam9x5_peripheral()
415 at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, u32 id, const struct clk_range *range, int chg_pid) at91_clk_register_sam9x5_peripheral() argument
H A Dpmc.h132 const struct clk_range *range, int chg_pid);
168 int chg_pid);
178 int chg_pid);
H A Ddt-compat.c140 int chg_pid = INT_MIN; in of_sama5d2_clk_generated_setup() local
157 chg_pid = GCK_INDEX_DT_AUDIO_PLL; in of_sama5d2_clk_generated_setup()
163 chg_pid); in of_sama5d2_clk_generated_setup()

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