Home
last modified time | relevance | path

Searched refs:cgr_val (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-gate2.c32 u8 cgr_val; member
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
90 u8 cgr_val, u8 cgr_mask) in clk_gate2_reg_is_enabled()
94 if (((val >> bit_idx) & cgr_mask) == cgr_val) in clk_gate2_reg_is_enabled()
109 gate->cgr_val, gate->cgr_mask); in clk_gate2_is_enabled()
138 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, in clk_hw_register_gate2()
154 gate->cgr_val = cgr_val; in clk_hw_register_gate2()
89 clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask) clk_gate2_reg_is_enabled() argument
136 clk_hw_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) clk_hw_register_gate2() argument
H A Dclk.h108 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
110 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
142 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
143 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
285 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
384 void __iomem *reg, u8 shift, u8 cgr_val, in __imx_clk_hw_gate2()
389 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count); in __imx_clk_hw_gate2()
383 __imx_clk_hw_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 cgr_val, unsigned long flags, unsigned int *share_count) __imx_clk_hw_gate2() argument
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-gate2.c32 u8 cgr_val; member
57 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
143 void __iomem *reg, u8 bit_idx, u8 cgr_val, in clk_hw_register_gate2()
159 gate->cgr_val = cgr_val; in clk_hw_register_gate2()
141 clk_hw_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) clk_hw_register_gate2() argument
H A Dclk.h71 cgr_val, clk_gate_flags, lock, share_count) \
73 cgr_val, clk_gate_flags, lock, share_count))
201 void __iomem *reg, u8 bit_idx, u8 cgr_val,
393 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) in imx_clk_gate2_cgr()
396 shift, cgr_val, 0, &imx_ccm_lock, NULL); in imx_clk_gate2_cgr()
392 imx_clk_gate2_cgr(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) imx_clk_gate2_cgr() argument

Completed in 3 milliseconds