Searched refs:cfgcr1 (Results 1 - 8 of 8) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll_mgr.c | 1132 i915_reg_t ctl, cfgcr1, cfgcr2; member
1145 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1151 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1157 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1187 intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1189 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1249 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1544 u32 ctrl1, cfgcr1, cfgcr in skl_ddi_hdmi_pll_dividers() local
2600 u32 cfgcr0, cfgcr1; cnl_ddi_hdmi_pll_dividers() local
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| H A D | intel_dpll_mgr.h | 188 u32 cfgcr1, cfgcr2; member
192 /* CNL also uses cfgcr1 */
199 * u32 cfgcr0, cfgcr1;
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| H A D | intel_display_debugfs.c | 943 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()
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| H A D | intel_display.c | 13996 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll_mgr.c | 1238 i915_reg_t ctl, cfgcr1, cfgcr2; member
1251 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1257 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1263 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1287 intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1289 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1347 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1689 dco_freq = (pll_state->cfgcr1 in skl_ddi_wrpll_get_freq()
1705 u32 ctrl1, cfgcr1, cfgcr2; skl_ddi_hdmi_pll_dividers() local
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| H A D | intel_dpll_mgr.h | 198 u32 cfgcr1, cfgcr2; member
211 * u32 cfgcr0, cfgcr1;
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| H A D | intel_display_debugfs.c | 668 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()
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| H A D | intel_display.c | 5323 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()
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