ccic_phy_parent_names (reference) in projects: kernel - OpenGrok search results

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Searched refs:ccic_phy_parent_names (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/mmp/
H A D	clk-of-pxa168.c	`187 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; variable 194 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},`
H A D	clk-of-pxa910.c	`193 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; variable 200 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},`
/kernel/linux/linux-6.6/drivers/clk/mmp/
H A D	clk-of-pxa168.c	`230 static const char * const ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; variable 240 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},`
H A D	clk-of-pxa910.c	`192 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; variable 199 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},`

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