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Help
Searched
refs:cachable
(Results
1 - 4
of
4
) sorted by relevance
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
H
A
D
los_mpu.c
72
BOOL
cachable
= 0;
in HalMpuRASRAddMemAttr()
local
77
cachable
= 1;
in HalMpuRASRAddMemAttr()
81
cachable
= 1;
in HalMpuRASRAddMemAttr()
85
cachable
= 0;
in HalMpuRASRAddMemAttr()
91
(*RASR) |= ((
cachable
<< MPU_RASR_C_Pos) | (buffable << MPU_RASR_B_Pos));
in HalMpuRASRAddMemAttr()
/kernel/liteos_m/arch/arm/cortex-m4/iar/
H
A
D
los_mpu.c
72
BOOL
cachable
= 0;
in HalMpuRASRAddMemAttr()
local
77
cachable
= 1;
in HalMpuRASRAddMemAttr()
81
cachable
= 1;
in HalMpuRASRAddMemAttr()
85
cachable
= 0;
in HalMpuRASRAddMemAttr()
91
(*RASR) |= ((
cachable
<< MPU_RASR_C_Pos) | (buffable << MPU_RASR_B_Pos));
in HalMpuRASRAddMemAttr()
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
H
A
D
los_mpu.c
72
BOOL
cachable
= 0;
in HalMpuRASRAddMemAttr()
local
77
cachable
= 1;
in HalMpuRASRAddMemAttr()
81
cachable
= 1;
in HalMpuRASRAddMemAttr()
85
cachable
= 0;
in HalMpuRASRAddMemAttr()
91
(*RASR) |= ((
cachable
<< MPU_RASR_C_Pos) | (buffable << MPU_RASR_B_Pos));
in HalMpuRASRAddMemAttr()
/kernel/liteos_m/arch/arm/cortex-m7/iar/
H
A
D
los_mpu.c
72
BOOL
cachable
= 0;
in HalMpuRASRAddMemAttr()
local
77
cachable
= 1;
in HalMpuRASRAddMemAttr()
81
cachable
= 1;
in HalMpuRASRAddMemAttr()
85
cachable
= 0;
in HalMpuRASRAddMemAttr()
91
(*RASR) |= ((
cachable
<< MPU_RASR_C_Pos) | (buffable << MPU_RASR_B_Pos));
in HalMpuRASRAddMemAttr()
Completed in 3 milliseconds