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Searched refs:bw_params (Results 1 - 25 of 59) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c436 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) in dcn314_build_watermark_ranges() argument
444 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
459 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn314_build_watermark_ranges()
462 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
505 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn314_notify_wm_ranges()
571 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn314_clk_mgr_helper_populate_bw_params() local
572 struct clk_limit_table_entry def_max = bw_params in dcn314_clk_mgr_helper_populate_bw_params()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c373 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table) in dcn315_build_watermark_ranges() argument
381 if (!bw_params->wm_table.entries[i].valid) in dcn315_build_watermark_ranges()
384 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn315_build_watermark_ranges()
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn315_build_watermark_ranges()
396 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn315_build_watermark_ranges()
399 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges()
442 dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn315_notify_wm_ranges()
477 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn315_clk_mgr_helper_populate_bw_params() local
479 struct clk_limit_table_entry def_max = bw_params in dcn315_clk_mgr_helper_populate_bw_params()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c344 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, in build_synthetic_soc_states() argument
365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
367 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) in build_synthetic_soc_states()
368 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in build_synthetic_soc_states()
369 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) in build_synthetic_soc_states()
370 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in build_synthetic_soc_states()
371 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz) in build_synthetic_soc_states()
372 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in build_synthetic_soc_states()
373 if (bw_params in build_synthetic_soc_states()
610 dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) dcn321_update_bw_bounding_box_fpu() argument
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H A Ddcn321_fpu.h32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn3_build_wm_range_table()
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()
119 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table()
120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_build_wm_range_table()
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()
123 clk_mgr->base.bw_params in dcn3_build_wm_range_table()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c195 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn302_fpu_update_bw_bounding_box() argument
220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params in dcn302_fpu_update_bw_bounding_box()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c191 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn303_fpu_update_bw_bounding_box() argument
216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params in dcn303_fpu_update_bw_bounding_box()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c97 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
118 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
150 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
155 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
160 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
253 if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) != in dcn3_update_clocks()
254 (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params in dcn3_update_clocks()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_update_soc_for_wm_a()
374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; in dcn30_fpu_update_soc_for_wm_a()
375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; in dcn30_fpu_update_soc_for_wm_a()
413 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
432 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_fpu_calculate_wm_and_dlg()
437 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
438 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; in dcn30_fpu_calculate_wm_and_dlg()
439 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; in dcn30_fpu_calculate_wm_and_dlg()
459 if (dc->clk_mgr->bw_params in dcn30_fpu_calculate_wm_and_dlg()
639 dcn30_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params, struct dc_bounding_box_max_clk *dcn30_bb_max_clk, unsigned int *dcfclk_mhz, unsigned int *dram_speed_mts) dcn30_fpu_update_bw_bounding_box() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c338 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) in dcn316_build_watermark_ranges() argument
346 if (!bw_params->wm_table.entries[i].valid) in dcn316_build_watermark_ranges()
349 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn316_build_watermark_ranges()
350 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn316_build_watermark_ranges()
361 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges()
364 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
407 dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn316_notify_wm_ranges()
478 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn316_clk_mgr_helper_populate_bw_params() local
500 bw_params in dcn316_clk_mgr_helper_populate_bw_params()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; in dcn32_build_wm_range_table_fpu()
192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
200 clk_mgr->base.bw_params in dcn32_build_wm_range_table_fpu()
2316 dcn32_patch_dpm_table(struct clk_bw_params *bw_params) dcn32_patch_dpm_table() argument
2448 build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) build_synthetic_soc_states() argument
2697 dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) dcn32_update_bw_bounding_box_fpu() argument
[all...]
H A Ddcn32_fpu.h62 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
70 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
185 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK); in dcn32_init_clocks()
189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn32_init_clocks()
191 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK); in dcn32_init_clocks()
196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn32_init_clocks()
198 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = in dcn32_init_clocks()
204 &clk_mgr_base->bw_params in dcn32_init_clocks()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c421 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) in dcn31_build_watermark_ranges() argument
429 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
447 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
490 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn31_notify_wm_ranges()
560 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn31_clk_mgr_helper_populate_bw_params() local
582 bw_params in dcn31_clk_mgr_helper_populate_bw_params()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c386 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) in vg_build_watermark_ranges() argument
394 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
456 vg_build_watermark_ranges(clk_mgr_base->bw_params, table); in vg_notify_wm_ranges()
563 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in vg_clk_mgr_helper_populate_bw_params() local
584 bw_params in vg_clk_mgr_helper_populate_bw_params()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c425 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) in build_watermark_ranges() argument
433 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
436 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
437 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
448 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
450 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
489 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
782 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) in rn_clk_mgr_helper_populate_bw_params() argument
805 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
807 for (i = 0; i < bw_params in rn_clk_mgr_helper_populate_bw_params()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c454 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) in build_watermark_ranges() argument
462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
477 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
479 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
518 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
639 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) in rn_clk_mgr_helper_populate_bw_params() argument
662 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
664 for (i = 0; i < bw_params in rn_clk_mgr_helper_populate_bw_params()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c456 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
457 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn31_update_soc_for_wm_a()
458 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn31_update_soc_for_wm_a()
459 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn31_update_soc_for_wm_a()
467 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
472 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn315_update_soc_for_wm_a()
474 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
580 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn31_update_bw_bounding_box() argument
583 struct clk_limit_table *clk_table = &bw_params in dcn31_update_bw_bounding_box()
658 dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) dcn315_update_bw_bounding_box() argument
719 dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) dcn316_update_bw_bounding_box() argument
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H A Ddcn31_fpu.h46 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
47 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c323 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn301_update_bw_bounding_box() argument
327 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_update_bw_bounding_box()
338 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_update_bw_bounding_box()
421 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn301_calculate_wm_and_dlg_fp() local
423 ASSERT(bw_params); in dcn301_calculate_wm_and_dlg_fp()
426 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn301_calculate_wm_and_dlg_fp()
429 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_calculate_wm_and_dlg_fp()
437 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_calculate_wm_and_dlg_fp()
442 table_entry = &bw_params in dcn301_calculate_wm_and_dlg_fp()
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/kernel/linux/linux-5.10/drivers/media/tuners/
H A Dtda18212.c36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
/kernel/linux/linux-6.6/drivers/media/tuners/
H A Dtda18212.c36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h83 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
85 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c182 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn314_update_bw_bounding_box_fpu() argument
184 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu()
198 if (bw_params->dram_channel_width_bytes > 0) in dcn314_update_bw_bounding_box_fpu()
199 dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn314_update_bw_bounding_box_fpu()
201 if (bw_params->num_channels > 0) in dcn314_update_bw_bounding_box_fpu()
202 dcn3_14_soc.num_chans = bw_params->num_channels; in dcn314_update_bw_bounding_box_fpu()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2239 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_calculate_wm_and_dlg_fp()
2244 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg_fp()
2245 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; in dcn30_calculate_wm_and_dlg_fp()
2246 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; in dcn30_calculate_wm_and_dlg_fp()
2266 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { in dcn30_calculate_wm_and_dlg_fp()
2267 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg_fp()
2268 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; in dcn30_calculate_wm_and_dlg_fp()
2269 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; in dcn30_calculate_wm_and_dlg_fp()
2286 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_calculate_wm_and_dlg_fp()
2290 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params in dcn30_calculate_wm_and_dlg_fp()
2459 dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) dcn30_update_bw_bounding_box() argument
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