| /kernel/linux/linux-5.10/drivers/staging/fbtft/ |
| H A D | fb_ili9481.c | 64 ROW_X_COL | HFLIP | VFLIP | (par->bgr << 3)); in set_var()
68 VFLIP | (par->bgr << 3)); in set_var()
72 ROW_X_COL | (par->bgr << 3)); in set_var()
76 HFLIP | (par->bgr << 3)); in set_var()
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| H A D | fb_hx8353d.c | 83 * rgb/bgr: in set_var()
85 * rgb h/w pin for color filter setting: 0=rgb, 1=bgr in set_var()
87 * rgb-bgr order color filter panel: 0=rgb, 1=bgr in set_var()
92 mx | my | (par->bgr << 3)); in set_var()
96 my | mv | (par->bgr << 3)); in set_var()
100 par->bgr << 3); in set_var()
104 mx | mv | (par->bgr << 3)); in set_var()
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| H A D | fb_ili9486.c | 62 0x80 | (par->bgr << 3)); in set_var()
66 0x20 | (par->bgr << 3)); in set_var()
70 0x40 | (par->bgr << 3)); in set_var()
74 0xE0 | (par->bgr << 3)); in set_var()
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| H A D | fb_st7735r.c | 112 MX | MY | (par->bgr << 3)); in set_var()
116 MY | MV | (par->bgr << 3)); in set_var()
120 par->bgr << 3); in set_var()
124 MX | MV | (par->bgr << 3)); in set_var()
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| H A D | fb_hx8340bn.c | 125 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, par->bgr << 3); in set_var()
129 MX | MV | (par->bgr << 3)); in set_var()
133 MX | MY | (par->bgr << 3)); in set_var()
137 MY | MV | (par->bgr << 3)); in set_var()
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| H A D | fb_ili9341.c | 90 MEM_X | (par->bgr << MEM_BGR)); in set_var()
94 MEM_V | MEM_L | (par->bgr << MEM_BGR)); in set_var()
98 MEM_Y | (par->bgr << MEM_BGR)); in set_var()
102 MEM_Y | MEM_X | MEM_V | (par->bgr << MEM_BGR)); in set_var()
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| H A D | fb_s6d02a1.c | 127 MX | MY | (par->bgr << 3)); in set_var()
131 MY | MV | (par->bgr << 3)); in set_var()
135 par->bgr << 3); in set_var()
139 MX | MV | (par->bgr << 3)); in set_var()
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| H A D | fb_ili9320.c | 193 write_reg(par, 0x3, (par->bgr << 12) | 0x30); in set_var()
196 write_reg(par, 0x3, (par->bgr << 12) | 0x28); in set_var()
199 write_reg(par, 0x3, (par->bgr << 12) | 0x00); in set_var()
202 write_reg(par, 0x3, (par->bgr << 12) | 0x18); in set_var()
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| H A D | fb_s6d1121.c | 98 write_reg(par, 0x03, 0x0003 | (par->bgr << 12)); in set_var()
101 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); in set_var()
104 write_reg(par, 0x03, 0x000A | (par->bgr << 12)); in set_var()
107 write_reg(par, 0x03, 0x0009 | (par->bgr << 12)); in set_var()
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| H A D | fb_ili9325.c | 183 write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); in set_var()
186 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); in set_var()
189 write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); in set_var()
192 write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); in set_var()
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| H A D | fb_ssd1331.c | 33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); in init_display()
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); in init_display()
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| H A D | fbtft.h | 53 * @set_var: Configure LCD with values from variables like @rotate and @bgr
128 * @bgr: LCD Controller BGR bit
138 bool bgr; member
188 * @bgr: BGR mode/\n
229 bool bgr; member
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| /kernel/linux/linux-6.6/drivers/staging/fbtft/ |
| H A D | fb_ili9481.c | 64 ROW_X_COL | HFLIP | VFLIP | (par->bgr << 3)); in set_var()
68 VFLIP | (par->bgr << 3)); in set_var()
72 ROW_X_COL | (par->bgr << 3)); in set_var()
76 HFLIP | (par->bgr << 3)); in set_var()
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| H A D | fb_hx8353d.c | 83 * rgb/bgr: in set_var()
85 * rgb h/w pin for color filter setting: 0=rgb, 1=bgr in set_var()
87 * rgb-bgr order color filter panel: 0=rgb, 1=bgr in set_var()
92 mx | my | (par->bgr << 3)); in set_var()
96 my | mv | (par->bgr << 3)); in set_var()
100 par->bgr << 3); in set_var()
104 mx | mv | (par->bgr << 3)); in set_var()
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| H A D | fb_st7735r.c | 112 MX | MY | (par->bgr << 3)); in set_var()
116 MY | MV | (par->bgr << 3)); in set_var()
120 par->bgr << 3); in set_var()
124 MX | MV | (par->bgr << 3)); in set_var()
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| H A D | fb_ili9486.c | 62 0x80 | (par->bgr << 3)); in set_var()
66 0x20 | (par->bgr << 3)); in set_var()
70 0x40 | (par->bgr << 3)); in set_var()
74 0xE0 | (par->bgr << 3)); in set_var()
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| H A D | fb_s6d02a1.c | 127 MX | MY | (par->bgr << 3)); in set_var()
131 MY | MV | (par->bgr << 3)); in set_var()
135 par->bgr << 3); in set_var()
139 MX | MV | (par->bgr << 3)); in set_var()
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| H A D | fb_hx8340bn.c | 125 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, par->bgr << 3); in set_var()
129 MX | MV | (par->bgr << 3)); in set_var()
133 MX | MY | (par->bgr << 3)); in set_var()
137 MY | MV | (par->bgr << 3)); in set_var()
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| H A D | fb_ili9341.c | 90 MEM_X | (par->bgr << MEM_BGR)); in set_var()
94 MEM_V | MEM_L | (par->bgr << MEM_BGR)); in set_var()
98 MEM_Y | (par->bgr << MEM_BGR)); in set_var()
102 MEM_Y | MEM_X | MEM_V | (par->bgr << MEM_BGR)); in set_var()
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| H A D | fb_s6d1121.c | 98 write_reg(par, 0x03, 0x0003 | (par->bgr << 12)); in set_var()
101 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); in set_var()
104 write_reg(par, 0x03, 0x000A | (par->bgr << 12)); in set_var()
107 write_reg(par, 0x03, 0x0009 | (par->bgr << 12)); in set_var()
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| H A D | fb_hx8347d.c | 96 write_reg(par, 0x16, MEM_V | MEM_X | (par->bgr << MEM_BGR)); in set_var()
99 write_reg(par, 0x16, par->bgr << MEM_BGR); in set_var()
102 write_reg(par, 0x16, MEM_V | MEM_Y | (par->bgr << MEM_BGR)); in set_var()
105 write_reg(par, 0x16, MEM_X | MEM_Y | (par->bgr << MEM_BGR)); in set_var()
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| H A D | fb_ili9320.c | 192 write_reg(par, 0x3, (par->bgr << 12) | 0x30); in set_var()
195 write_reg(par, 0x3, (par->bgr << 12) | 0x28); in set_var()
198 write_reg(par, 0x3, (par->bgr << 12) | 0x00); in set_var()
201 write_reg(par, 0x3, (par->bgr << 12) | 0x18); in set_var()
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| H A D | fb_ili9325.c | 183 write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); in set_var()
186 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); in set_var()
189 write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); in set_var()
192 write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); in set_var()
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| H A D | fb_ssd1331.c | 33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); in init_display()
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); in init_display()
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| H A D | fbtft.h | 53 * @set_var: Configure LCD with values from variables like @rotate and @bgr
128 * @bgr: LCD Controller BGR bit
138 bool bgr; member
188 * @bgr: BGR mode/\n
229 bool bgr; member
|