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Searched refs:armada_reg_queue_set (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/armada/
H A Darmada_overlay.c100 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); in armada_drm_overlay_plane_atomic_update()
103 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); in armada_drm_overlay_plane_atomic_update()
106 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); in armada_drm_overlay_plane_atomic_update()
115 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0), in armada_drm_overlay_plane_atomic_update()
117 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1), in armada_drm_overlay_plane_atomic_update()
119 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2), in armada_drm_overlay_plane_atomic_update()
121 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0), in armada_drm_overlay_plane_atomic_update()
123 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1), in armada_drm_overlay_plane_atomic_update()
125 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2), in armada_drm_overlay_plane_atomic_update()
129 armada_reg_queue_set(reg in armada_drm_overlay_plane_atomic_update()
[all...]
H A Darmada_plane.c190 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN); in armada_drm_primary_plane_atomic_update()
193 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN); in armada_drm_primary_plane_atomic_update()
196 armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN); in armada_drm_primary_plane_atomic_update()
201 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0), in armada_drm_primary_plane_atomic_update()
203 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0), in armada_drm_primary_plane_atomic_update()
H A Darmada_crtc.h27 #define armada_reg_queue_set(_r, _i, _v, _o) \ macro
H A Darmada_crtc.c353 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); in armada_drm_crtc_mode_set_nofb()
378 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); in armada_drm_crtc_mode_set_nofb()
379 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); in armada_drm_crtc_mode_set_nofb()
380 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); in armada_drm_crtc_mode_set_nofb()
381 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, in armada_drm_crtc_mode_set_nofb()
/kernel/linux/linux-6.6/drivers/gpu/drm/armada/
H A Darmada_overlay.c103 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN); in armada_drm_overlay_plane_atomic_update()
106 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); in armada_drm_overlay_plane_atomic_update()
109 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN); in armada_drm_overlay_plane_atomic_update()
118 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0), in armada_drm_overlay_plane_atomic_update()
120 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1), in armada_drm_overlay_plane_atomic_update()
122 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2), in armada_drm_overlay_plane_atomic_update()
124 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0), in armada_drm_overlay_plane_atomic_update()
126 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1), in armada_drm_overlay_plane_atomic_update()
128 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2), in armada_drm_overlay_plane_atomic_update()
133 armada_reg_queue_set(reg in armada_drm_overlay_plane_atomic_update()
[all...]
H A Darmada_plane.c171 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN); in armada_drm_primary_plane_atomic_update()
174 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN); in armada_drm_primary_plane_atomic_update()
177 armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN); in armada_drm_primary_plane_atomic_update()
182 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0), in armada_drm_primary_plane_atomic_update()
184 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0), in armada_drm_primary_plane_atomic_update()
H A Darmada_crtc.h27 #define armada_reg_queue_set(_r, _i, _v, _o) \ macro
H A Darmada_crtc.c352 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); in armada_drm_crtc_mode_set_nofb()
377 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); in armada_drm_crtc_mode_set_nofb()
378 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); in armada_drm_crtc_mode_set_nofb()
379 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); in armada_drm_crtc_mode_set_nofb()
380 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, in armada_drm_crtc_mode_set_nofb()

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