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Searched refs:__offset_STAGE (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h343 static inline uint32_t __offset_STAGE(uint32_t idx) in __offset_STAGE() function
353 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE()
355 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_OP()
375 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_FG_ALPHA()
377 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_BG_ALPHA()
379 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
381 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
383 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
385 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h350 static inline uint32_t __offset_STAGE(uint32_t idx) in __offset_STAGE() function
360 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE()
362 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_OP()
382 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_FG_ALPHA()
384 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_BG_ALPHA()
386 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
388 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
390 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
392 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()

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